參數(shù)資料
型號： MC145423DT
廠商： Freescale Semiconductor
文件頁數(shù)： 2/15頁
文件大?。?/td> 0K
描述： IC TXRX UDLT/ISDN 28TSSOP
標準包裝： 50
類型： 收發(fā)器
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 28-TSSOP
包裝： 管件
MC145423
TELECOMMUNICATIONS
18
* Tx is high impedance when TE1 and TE2 are both low, simultaneously.
Tx is undefined when TE1 and TE2 are both high, simultaneously.
10
SDO1
Output
16 kbps
Data Out
16 kbps
Data Out
Data Not
Changed
16 kbps
Data Out
Data Not
Changed
16 kbps
Data Out
11
SDO2
Output
16 kbps
Data Out
16 kbps
Data Out
Data Not
Changed
16 kbps
Data Out
Data Not
Changed
16 kbps
Data Out
12
SE/
(Mu/A)
Input
1/0
Mu/A
1/0
Mu/A
1/0
Mu/A
1/0
Mu/A
1/0
Mu/A
1/0
Mu/A
13
PD
I/O
110000
14
MOD
TRI/SQ
Input
111111
15
Tx
Output
128 kbps
Data Out*
128 kbps
Data Out*
High
Impedance
64 kbps
Data Out
500 Hz
Tone Out
500 Hz
Tone Out
16
EN2-TE2/
SIE/B1B2
Output
EN2 8 kHz
EN2 = 0
EN2 8 kHz
17
EN1-TE1
Output
EN1 8 kHz
EN1 = 0
EN1 8 kHz
18
MSI/
TONE
Input
1/0 Tone
0 No Tone
1 No Tone
1 Tone
19
CCI/
XTALin
Input
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
20
TDC-RDC/
XTALout
Output
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
XTAL
8.192 MHz
21
LI SENS/
2.048 MHz
Output
2.048 MHz
22
RE1/
CLKOUT
Output
RE1 8 kHz
RE1 0
RE1 8 kHz
23
RE2/
BCLK
Output
BCLK
128 kHz
BCLK = 0
BCLK
128 kHz
BCLK
128 kHz
BCLK
128 kHz
BCLK
128 kHz
24
Rx
Input
128 kbps
Data In
Don’t Care
128 kbps
Data In
128 kbps
Data In
25
LO2
Output
Modulator
Out
Modulator
Out
LO2 = LO1
26
LO1
Output
Modulator
Out
Modulator
Out
LO2 = LO1
LO1 = LO2
27
MASTER/
SLAVE
Input
111111
28
VDD
Power
+V
+V+V+V+V
MC145423 UDLT-3 PIN STATES FOR UDLT-2 SLAVE MODE (continued)
MC145423
UDLT-2 Slave Mode
Powered-Up
UDLT-2 Slave Mode
Powered-Down
TONE = 0, Off
TONE = 1, On
Pin
No.
Pin
Name
In/out
Normal
LB Low
No Valid
Burst Rec’d
Valid
Burst Rec’d
No Valid
Burst Rec’d
Valid
Burst Rec’d
TELECOMMUNICATIONS
19
MC145423
* Tx is high impedance when TE1 and TE2 are both low, simultaneously.
Tx is undefined when TE1 and TE2 are both high, simultaneously.
MC145423 UDLT-3 PIN STATES FOR UDLT-2 MASTER MODE
MC145423
UDLT-2 Master Powered-Up
UDLT-2 Master Powered-Down
Pin
No.
Pin
Name
In/out
Normal
LB Low
SE Low
Normal
SE Low
1VSS
Power
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
2Vref
Analog Ref
AGND VDD/2
3
LI
Input
Analog In
Don’t Care
Analog In
4LB
Input
1
0
State Latched
Don’t Care
5
VD
Output
Digital Out
High Impedance
Digital Out
High Impedance
6
SDI1
Input
16 kbps Data In
State Latched
16 kbps Data In
State Latched
7
SDI2
Input
16 kbps Data In
State Latched
16 kbps Data In
State Latched
8
FRAME 10/
20
Input
11111
9
SDCLK
Input
16 kHz
10
SDO1
Output
16 kbps Data
Out
16 kbps Data
Out
High Impedance
16 kbps Data
Out
High Impedance
11
SDO2
Output
16 kbps Data
Out
16 kbps Data
Out
High Impedance
16 kbps Data
Out
High Impedance
12
SE/(Mu/A)
Input
11010
13
PD
Input
1
State Latched
0
State Latched
14
MOD TRI/SQ
Input
11111
15
Tx
Output
128 kbps*
Data Out
128 kbps*
Data Out
128 kbps*
Data Out
128 kbps*
Data Out
128 kbps*
Data Out
16
EN2-TE2/
SIE/B1B2
Input
TE2 8 kHz
17
EN1-TE1
Input
TE1 8 kHz
18
MSI/TONE
Input
8 kHz
19
CCI/XTALin
Input
CCI
4.096 MHz
CCI
4.096 MHz
CCI
4.096 MHz
CCI
4.096 MHz
CCI
4.096 MHz
20
TDC-RDC/
XTALout
Input
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
21
LI SENS/
2.048 MHz
Input
Digital In
Sensitivity
Digital In
Sensitivity
Digital In
Sensitivity
Digital In
Sensitivity
Digital In
Sensitivity
22
RE1/
CLKOUT
Input
RE1 8 kHz
23
RE2/BCLK
Input
RE2 8 kHz
24
Rx
Input
128 kbps Data In 128 kbps Data In 128 kbps Data In
Don’t Care
25
LO2
Output
Modulator Out
LO2 = LO1
No Effect
LO2 = LO1
26
LO1
Output
Modulator Out
LO1 = LO2
No Effect
LO1 = LO2
27
MASTER/
SLAVE
Input
00000
28
VDD
Power
+V+V+V+V+V
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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