參數(shù)資料
型號(hào): MC33389CDHR2
廠商: Freescale Semiconductor
文件頁數(shù): 27/49頁
文件大小: 0K
描述: IC SYSTEM BASE W/CAN 20-HSOP
標(biāo)準(zhǔn)包裝: 750
控制器類型: 系統(tǒng)基礎(chǔ)芯片(SBC),CAN
接口: SPI 串行
電源電壓: 5V
電流 - 電源: 3.5mA
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.433",11.00mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 20-HSOP
包裝: 帶卷 (TR)
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
33389
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 19 illustrates content of the HC08/12 SPI Data
Register and the SBC SPI Data Register before the
transmission. The new address and R/W bits are already in
the SPI Data Register while the new data and parity bits are
still in an appropriate microcontroller register or memory. This
second byte has to be loaded into the HC08/12 SPI Data
Register after the first byte was transmitted to the SBC.
Figure 19. Microcontroller SPI Reading Data - Sequence A
After transmission of the first byte, the HC08/12 SPI read buffer contains the old address and R/W bits received from the SBC.
An appropriate operation in the microcontroller loads the new data and parity into the HC08/12 SPI Data Register (second byte).
In the SBC the internal logic loads P3-P0 and D3-D0 to the location of Bit 15 to Bit 8 in the SBC SPI Data Register, shifting this
data within the remaining eight clock cycles. Please see Figure 20.
Figure 20. Microcontroller SPI Reading Data - Sequence B
After sixteen clock cycles, the microcontrollers read buffer contains the new parity, and data and is now ready for the next
transmission. Please see Figure 21.
A5 A4 A3 A2 A1 A0
D3 D2 D1 D0
P3 P2 P1 P0
RW
A3 A2 A1 A0
0
A5 A4
00
SBC SPI Data Register
Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HC08/12 SPI Data Register
old address + R/W
old data
old parity
new address + R/W (1st byte)
new data + parity (2nd byte)
A5 A4 A3 A2 A1 A0
D3 D2 D1 D0
P3 P2 P1 P0
0
00
0000
00
SBC SPI Data Register
Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
HC08/12 SPI Data Register
new address + R/W
new data
new parity
addressed by the new address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
A3 A2 A1 A0 RW RW
A5 A4
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
old address + R/W in
HC08/12 SPI read buffer
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