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| 型號： | MC33394DH |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 4/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC POWER SUPPLY MULT-OUT 44-HSOP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 應(yīng)用： | Motorola MPC55x、MPC56x 微處理器 |
| 接口： | SPI 串行 |
| 電源電壓： | 4 V ~ 26.5 V |
| 封裝/外殼： | 44-BSSOP（0.433"，11.00mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 44-HSOP |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
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33394
12
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
3. ELECTRICAL CHARACTERISTICS (–40
°C ≤ TA ≤ +125°C; +4.0 V ≤ VBAT ≤ +26.5 V using the 33394 typical application
circuit – see Figure 1, unless otherwise noted.)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
DC CHARACTERISTICS:
SUPERVISORY OUTPUTS
Reset Voltage Thresholds
/HRESET to follow /PRERESET by 0.7
s
VDDH Reset Upper Threshold Voltage
(Note 1)
5.2
V
VDDH Reset Lower Threshold Voltage
(Note 1)
4.8
V
VDD3_3 Reset Upper Threshold Voltage
(Note 1)
3.43
V
VDD3_3 Reset Lower Threshold Voltage
(Note 1)
3.17
V
VDDL Reset Upper Threshold Voltage
(Notes 1, 4)
1.35
V
VDDL Reset Lower Threshold Voltage
(Notes 1, 4)
1.2
V
/PORESET Voltage Threshold
VKAM Reset Upper Threshold Voltage
(Notes 2, 5)
1.35
V
VKAM Reset Lower Threshold Voltage
(Notes 2, 5)
1.2
V
/PRERESET, /HRESET, /PORESET Open Drain Maximum Voltage
(Note 3)
7.0
V
/PRERESET, /HRESET, /PORESET Open Drain Pull–Down Current,
Vreset< 0.4 V
1.0
mA
/PRERESET, /HRESET, /PORESET Low–Level Output Voltage,
IOL = 1.0 mA
0.5
V
/PRERESET /HRESET /PORESET Leakage Current
15
A
WAKEUP High–Level Output Voltage, IOH = –800
A
VDDH–0.8
V
WAKEUP Low–Level Output Voltage, IOL = 1.6 mA
0.4
V
HRT Voltage Threshold
2.49
2.53
2.57
V
HRT Sink Current
1.0
mA
HRT Leakage Current
5.0
A
HRT Saturation Voltage, HRT Current = 1 mA
0.4
V
AC CHARACTERISTICS:
SUPERVISORY OUTPUTS
/PORESET Delay
Delay time from VKAM in regulation and stable to the release of
/PORESET
7.0
10
15
ms
Reset Delay Time
Time from fault on VDDH, VDD3_3, VDDL or VKAM to Reset
(/PORESET, /PRERESET)
10
20
50
s
/HRESET Delay Time
Time From /PRERESET low to /HRESET low
0.5
0.7
1.0
s
VDDH, VDDL, VREF Power Up Sequence
Max Power Up Sequence Time Dependent on Output Load
Characteristics.
(Note 3)
800
s
NOTE:
1. VDDH, VDD3_3, VDDL regulator outputs supervised by /PRERESET and /HRESET.
2. VKAM regulator output supervised by /PORESET.
3. Guaranteed by design but not production tested.
4. Measured at the VDDL_FB pin.
5. Measured at the VKAM_FB pin.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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