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參數(shù)資料
| 型號： | MC33991 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Gauge Driver Integrated Circuit(標尺驅(qū)動器集成電路) |
| 中文描述： | 儀表驅(qū)動集成電路（標尺驅(qū)動器集成電路） |
| 文件頁數(shù)： | 12/36頁 |
| 文件大?。?/td> | 660K |
| 代理商： | MC33991 |
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33991
12
Go to: www.freescale.com
PC33991 SPI INTERFACE AND PROTOCOL DESCRIPTION
INTRODUCTION
The SPI interface has full duplex, three wire synchronous,
16-bit serial synchronous interface data transfer and four I/O
lines associated with it: (SI, SO, SCLK, and CS). The SI/SO
pins of the 33991 follows a first in/first out (D15/D0) protocol
with both input and output words transferring the most
significant bit first. All inputs are compatible with 5.0 V CMOS
logic levels.
DETAILED SIGNAL DESCRIPTIONS
Chip Select (CS)
The Chip Select (CS) pin enables communication with the
Master device. When this pin is in a logic [0] state, the GDIC is
capable of transferring information to, and receivinginformation
from, the Master. The 33991latches data in from the input shift
registers to the addressed registers on the rising edge of CS.
The output driver on the SO pin is enabled when CS is logic [0].
When CS is logic high, signals at the SCLK and SI pins are
ignored; the SO pin is tri-stated (high impedance). CS will only
be transitioned from a logic [1] state to a logic [0] state when
SCLK is a logic [0]. CS has an internal pull-up (
lup)
connected
to the pin as specified in the Control I/O table.
Serial Clock (SCLK)
SCLK clocks the internal shift registers of the 33991device.
The serial input (SI) pin accepts data into the Input Shift register
on the falling edge of the SCLKsignal while the serial output pin
(SO) shifts data information out of the SO Line Driver on the
rising edge of the SCLK signal. It is important the SCLK pin be
in a logic[0] state whenever the CSmakesany transition.SCLK
has an internal pull down (
Idwn
), specified in the Control I/O
table. When CS is logic [1], signals at the SCLK and SI pins are
ignored; SO is tri-stated (high impedance). See the Data
Transfer Timing diagrams in s 2 and 3.
Serial Input (SI)
This pin is the input of the Serial Peripheral Interface (SPI).
Serial Input (SI) information is read on the falling edge of SCLK.
A 16-bit stream of serial data is required on the SI pin, starting
with the most significant bit (MSB). Messages not multiples of
16 bits (e.g. daisy chained device messages) are ignored. After
transmitting a 16-bit word, the CS pin has to be deasserted
(logic [1]) before transmitting a new word. SI information is
ignored when CS is in a logic high state.
Serial Output (SO)
The Serial Output (SO) data pin is a tri-stateable output from
the shift register. The status register bits are the first 16-bits
shiftedout. Those bitsarefollowed bythemessagebitsclocked
in FIFO, when the device is in a daisy chain connection, or
being sent words multiples of 16 bits. Data is shifted on the
rising edge of the SCLK signal. The SO pin remains in a high
impedance state until the CS pin is put into a logic low state.
SYSTEM APPLICATION INFORMATION
This section provides a description of the 33991device SPI
behavior. To follow the explanations below, please refer to the
timing diagrams illustrated in Figures 4 and 5.
Table 1. Data Transfer Timing
Pin
Description
CS (1-to-0)
SO pin is enabled
CS (0-to-1)
33991configuration and desired output states are transferred and executed according to the data in the
shift registers
SO
Will change state on the rising edge of the SCLK pin signal
SI
Will accept data on the falling edge of the SCLK pin signal
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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