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| 型號： | MC56F8036VLF |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 15/164頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL SGNL CTLR 16BIT 48-LQFP |
| 標準包裝： | 1,250 |
| 系列： | 56F8xxx |
| 核心處理器： | 56800E |
| 芯體尺寸： | 16-位 |
| 速度： | 32MHz |
| 連通性： | CAN，I²C，SCI，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 39 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b; D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 734 (CN2011-ZH PDF) |
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Clocks
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
111
The deassertion sequence of internal resets coordinates the device start up, including the clocking system
start up. The sequence is described in the following steps:
1. As power is applied, the Relaxation Oscillator starts to operate. When a valid operating voltage is
reached, the POR reset will release.
2. The release of POR reset permits operation of the POR reset extender. The POR extender generates
an extended POR reset, which is released 64 OSC_CLK cycles after POR reset. This provides an
additional time period for the clock source and power to stabilize.
3. A Combined reset consists of the OR of the extended POR reset, the external reset, the COP reset
and Software reset. The entire device, except for the POR extender, is held reset as long as
Combined reset is asserted. The release of Combined reset permits operation of the CTRL register,
the Synchronous reset generator, and the CLKGEN reset extender.
4. The Synchronous reset generator generates a reset to the Software and COP reset logic. The COP
and Software reset logic is released three OSC_CLK cycles after Combined reset deasserts. This
provides a reasonable minimum duration to the reset for these specialized functions.
5. The CLKGEN reset extender generates the CLKGEN reset used by the clock generation logic. The
CLKGEN reset is released 32 OSC_CLK cycles after Combined reset deasserts. This provides a
window in which the SIM stabilizes the master clock inputs to the clock generator.
6. The release of CLKGEN reset permits operation of the clock generation logic and the Peripheral
reset extender. The Peripheral reset extender generates the Peripheral reset, which is released 32
SYS_CLK cycles after CLKGEN reset. This provides a window in which peripheral and core logic
remain clocked, but in reset, so that synchronous resets can be resolved.
7. The release of Peripheral reset permits operation of the peripheral logic and the Core reset extender.
The Core reset extender generates the Core reset, which is released 32 SYS_CLK cycles after the
Peripheral reset. This provides a window in which critical peripheral start-up functions, such as
Flash Security in the Flash memory, can be implemented.
8. The release of Core reset permits execution of code by the 56800E core and marks the end of the
system start-up sequence.
Figure 6-29 illustrates clock relationships to one another and to the various resets as the device comes out
of reset. RST is assumed to be the logical AND of all active-low system resets (for example, POR, external
reset, COP and Software reset). In the 56F8036, this signal will be stretched by the SIM for a period of
time (up to 96 OSC_CLK clock cycles, depending upon the status of the POR) to create the clock
generation reset signal (CLKGEN_RST). The SIM should deassert CLKGEN_RST synchronously with
the negative edge of OSC_CLK in order to avoid skew problems. CLKGEN_RST is delayed 32 SYS_CLK
cycles to create the peripheral reset signal (PERIP_RST). PERIP_RST is then delayed by 32 SYS_CLK
cycles to create CORE_RST. Both PERIP_RST and CORE_RST should be released on the negative edge
of SYS_CLK_D as shown. This phased releasing of system resets is necessary to give some peripherals
(for example, the Flash interface unit) set-up time prior to the 56800E core becoming active.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC56F8036VLF | 制造商:Freescale Semiconductor 功能描述:IC DSC 64KB 32MHZ 3.6V LQFP-48 |
| MC56F8037 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8037EVM | 功能描述:開發(fā)板和工具包 - 其他處理器 MC56F8037 EVAL BOARD RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MC56F8037EVM | 制造商:Freescale Semiconductor 功能描述:MC56F8037 EVALUATION BRD |
| MC56F8037MLH | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT DSPHC RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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