參數(shù)資料
型號: MC56F8036VLF
廠商: Freescale Semiconductor
文件頁數(shù): 9/164頁
文件大?。?/td> 0K
描述: IC DGTL SGNL CTLR 16BIT 48-LQFP
標準包裝: 1,250
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: CAN,I²C,SCI,SPI
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 39
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 734 (CN2011-ZH PDF)
56F8036 Data Sheet, Rev. 6
106
Freescale Semiconductor
Figure 6-27 Internal Peripheral Source Select Register for TMRA (SIM_IPS2)
6.3.23.1
Reserved—Bits 15–13
This bit field is reserved. Each bit must be set to 0.
6.3.23.2
Select Input Peripheral Source for TA3 (IPS2_TA3)—Bit 12
This field selects the alternate input peripheral source signal to feed Quad Timer A, input 3.
0 = I/O pin (External) - Use Timer A3 input/output pin
1 = PWM SYNC (Internal) - Use PWM reload synchronization signal
6.3.23.3
Reserved—Bits 11–9
This bit field is reserved. Each bit must be set to 0.
6.3.23.4
Select Input Peripheral Source for TA2 (IPS2_TA2)—Bit 8
This field selects the alternate input source signal to feed Quad Timer A, input 2.
0 = I/O pin (External) - Use Timer A2 input/output pin
1 = CMPBO (Internal) - Use Comparator B output
6.3.23.5
Reserved—Bits 7–5
This bit field is reserved. Each bit must be set to 0.
6.3.23.6
Select Input Peripheral Source for TA1 (IPS2_TA1)—Bit 4
This field selects the alternate input peripheral source signal to feed Quad Timer A, input 1.
0 = I/O pin (External) - Use Timer A1 input/output pin
1 = CMPAO (Internal) - Use Comparator A output
6.3.23.7
Reserved—Bits 3–0
This bit field is reserved. Each bit must be set to 0.
For Timer A to detect the PWM SYNC signal, the clock rate of both the PWM module and Timer A
module must be identical, at either the system clock rate or 3X system clock rate.
Base + $1A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
IPS2_
TA3
0
IPS2_
TA2
0
IPS2_
TA1
0
Write
RESET
0
0000000
0000
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