參數(shù)資料
型號: MC56F8147VPYE
廠商: Freescale Semiconductor
文件頁數(shù): 161/172頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 40MHZ 160-LQFP
標(biāo)準(zhǔn)包裝: 40
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 40MHz
連通性: EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 76
程序存儲(chǔ)器容量: 128KB(64K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 160-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 734 (CN2011-ZH PDF)
Register Descriptions
56F8347 Technical Data, Rev.11
Freescale Semiconductor
89
Preliminary
5.6.7.5
Timer D, Channel 0 Interrupt Priority Level (TMRD0 IPL)—Bits 7–6
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.6
Reserved—Bits 5–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.7.7
Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level
(DEC0_XIRQ IPL)—Bits 3–2
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.7.8
Quadrature Decoder 0, HOME Signal Transition or Watchdog Timer
Interrupt Priority Level (DEC0_HIRQ IPL)—Bits 1–0
This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
5.6.8
Interrupt Priority Register 7 (IPR7)
Figure 5-10 Interrupt Priority Register (IPR7)
Base + $7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
TMRA0 IPL
TMRB3 IPL
TMRB2 IPL
TMRB1 IPL
TMRB0 IPL
TMRC3 IPL
TMRC2 IPL
TMRC1 IPL
Write
RESET
00000
0000000
0000
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