Note: The 160 Map Ball Grid Array is not available in the " />
參數(shù)資料
型號: MC56F8147VPYE
廠商: Freescale Semiconductor
文件頁數(shù): 64/172頁
文件大?。?/td> 0K
描述: IC DSP 16BIT 40MHZ 160-LQFP
標(biāo)準(zhǔn)包裝: 40
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 40MHz
連通性: EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 76
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 160-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 734 (CN2011-ZH PDF)
56F8347 Technical Data, Rev.11
156
Freescale Semiconductor
Preliminary
Part 11 Packaging
Note: The 160 Map Ball Grid Array is not available in the 56F8147 device.
11.1 56F8347 Package and Pin-Out Information
This section contains package and pin-out information for the 56F8347. This device comes in a 160-pin
Low-profile Quad Flat Pack (LQFP) and 160 Map Ball Grid Array. Figure 11-1 shows the package
lay-out for the 160-pin LQFP, and Figure 11-2 for the160 Map Ball Grid Array. Figure 11-5 for the shows
the mechanical parameters for the LQFP package and Figure 11-3 for the MBGA. Table 11-1 lists the
pin-out for the 160-pin LQFP and Table 11-2 lists the pin-out for the 160 MBGA.
Figure 11-1 Top View, 56F8347 160-Pin LQFP Package
VDD_IO
VPP2
CLKO
TXD0
RXD0
PHASEA1
PHASEB1
INDEX1
HOME1
A1
A2
A3
A4
A5
VCAP4*
VDD_IO
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
VSS
D7
D8
D9
VDD_IO
D10
GPIOB0
GPIOB1
GPIOB2
GPIOB3
Pin 1
Orientation Mark
121
41
GPIOB4
PWMB0
PWMB1
PWMB2
V
SS
EM
I_
MO
DE
HO
ME
0
IN
D
E
X
0
PH
ASE
B0
PH
AS
EA0
A0
D15
D1
4
D13
D12
D1
1
MO
SI
0
MI
SO
0
SCL
K
0
SS
0
V
CA
P
2*
C
A
N_
RX
CA
N_TX
V
PP
1
TDO
TDI
TM
S
TCK
TRST
TC
1
V
DD_
IO
TC0
TD3
TD2
TD1
TD0
ISA
2
IS
A1
IS
A0
V
SS
EX
T
B
O
T
AN
B
7
AN
B6
AN
B5
V
SS
V
DD
_I
O
PW
MB
3
PW
M
B
4
PW
MB
5
GP
IOB5
GP
IOB6
G
P
IOB
7
TXD1
RX
D1
WR
RD
PS
DS
GP
IOD0
G
P
IOD1
G
P
IOD2
GPI
O
D3
GP
IOD4
GPIO
D5
IS
B0
V
CA
P
1*
ISB
1
ISB2
IRQA
IR
Q
B
FA
U
LT
B
0
FA
U
LT
B
1
FA
U
LT
B
2
D0
D1
FA
U
LT
B
3
PW
MA0
V
SS
PW
M
A
1
PW
M
A
2
V
DD_
IO
PW
M
A
3
PW
M
A
4
V
SS
ANB4
ANB3
ANB2
ANB1
ANB0
VSSA_ADC
VDDA_ADC
VREFH
VREFP
VREFMID
VREFN
VREFLO
TEMP_SENSE
ANA7
ANA6
ANA5
ANA4
ANA3
ANA2
ANA1
ANA0
CLKMODE
RESET
RSTO
VDD_IO
VCAP3*
EXTAL
XTAL
VDDA_OSC_PLL
OCR_DIS
D6
D5
D4
FAULTA3
D3
FAULTA2
FAULTA1
D2
FAULTA0
PWMA5
81
* When the on-chip regulator is disabled, these four pins become 2.5V VDD_CORE.
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