參數(shù)資料
型號： MC56F8147VPYE
廠商： Freescale Semiconductor
文件頁數(shù)： 28/172頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 40MHZ 160-LQFP
標(biāo)準(zhǔn)包裝： 40
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 40MHz
連通性： EBI/EMI，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 76
程序存儲器容量： 128KB（64K x 16）
程序存儲器類型： 閃存
RAM 容量： 4K x 16
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 160-LQFP
包裝： 托盤
產(chǎn)品目錄頁面： 734 (CN2011-ZH PDF)
Introduction
56F8347 Technical Data, Rev.11
Freescale Semiconductor
123
Preliminary
7.2.4
Product Analysis
The recommended method of unsecuring a programmed device for product analysis of field failures is via
the backdoor key access. The customer would need to supply Technical Support with the backdoor key
and the protocol to access the backdoor routine in the Flash. Additionally, the KEYEN bit that allows
backdoor key access must be set.
An alternative method for performing analysis on a secured microcontroller would be to mass-erase and
reprogram the Flash with the original code, but modify the security bytes.
To insure that a customer does not inadvertently lock himself out of the device during programming, it is
recommended that he program the backdoor access key first, his application code second, and the security
bytes within the FM configuration field last.
Part 8 General Purpose Input/Output (GPIO)
8.1 Introduction
This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User
Manual and contains only chip-specific information. This information supercedes the generic information
in the 56F8300 Peripheral User Manual.
8.2 Memory Maps
The width of the GPIO port defines how many bits are implemented in each of the GPIO registers. Based
on this and the default function of each of the GPIO pins, the reset values of the GPIOx_PUR and
GPIOx_PER registers change from port to port. Tables 4-29 through 4-34 define the actual reset values of
these registers.
8.3 Configuration
There are six GPIO ports defined on the 56F8347/56F8147. The width of each port and the associated
peripheral function is shown in Table 8-1 and Table 8-2. The specific mapping of GPIO port pins is
shown in Table 8-3.
Table 8-1 56F8347 GPIO Ports Configuration
GPIO
Port
Width
Available
Pins in
56F8347
Peripheral Function
Reset Function
A14
14
14 pins - EMI Address pins
EMI Address
B8
8
8 pins - EMI Address pins
EMI Address
C11
11
4 pins -DEC1 / TMRB / SPI1
4 pins -DEC0 / TMRA
3 pins -PWMA current sense
DEC1 / TMRB
DEC0 / TMRA
PWMA current sense
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