參數(shù)資料
型號： MC56F8147VVFE
廠商： Freescale Semiconductor
文件頁數(shù)： 91/172頁
文件大小： 0K
描述： IC DGTL SIGNAL CTLR 160-MAPBGA
標準包裝： 126
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 40MHz
連通性： EBI/EMI，SCI，SPI
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 76
程序存儲器容量： 128KB（64K x 16）
程序存儲器類型： 閃存
RAM 容量： 4K x 16
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉換器： A/D 16x12b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 160-BGA
包裝： 托盤
Signal Pins
56F8347 Technical Data, Rev.11
Freescale Semiconductor
25
Preliminary
WR
51
L4
Output
In reset,
output is
disabled,
pull-up is
enabled
Write Enable — WR is asserted during external memory
write cycles. When WR is asserted low, pins D0 - D15
become outputs and the device puts data on the bus. When
WR is deasserted high, the external data is latched inside
the external device. When WR is asserted, it qualifies the A0
- A16, PS, and DS pins. WR can be connected directly to the
WE pin of a static RAM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), WR is tri-stated when the external bus is
inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in
the SIM_PUDR register.
PS
(CS0)
(GPIOD8)
53
N6
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Program Memory Select — This signal is actually CS0 in
the EMI, which is programmed at reset for compatibility with
the 56F80x PS signal. PS is asserted low for external
program memory access.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), CS0 is tri-stated when the external bus is
inactive.
CS0 resets to provide the PS function as defined on the
56F80x devices.
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOD_PUR register.
DS
(CS1)
(GPIOD9)
54
L5
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Data Memory Select — This signal is actually CS1 in the
EMI, which is programmed at reset for compatibility with the
56F80x DS signal. DS is asserted low for external data
memory access.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), A0 - A23 and EMI control signals are
tri-stated when the external bus is inactive.
CS1 resets to provide the DS function as defined on the
56F80x devices.
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
To deactivate the internal pull-up resistor, clear bit 9 in the
GPIOD_PUR register.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
Signal Name
Pin
No.
Ball
No.
Type
State
During
Reset
Signal Description
相關PDF資料
PDF描述
MAC7101MAG40 IC MCU 32BIT FLASH 144-LQFP
KMC9328MX1DVM20 IC MCU I.MX 200MHZ 256-MAPBGA
KMC9328MX1CVM15 IC MCU I.MX 150MHZ 256-PBGA
MC9S12C96CFUER IC MCU 16BIT 4K FLASH 80-QFP
MC705B16NCFNER IC MCU 8BIT 15K OTP 52-PLCC
相關代理商/技術參數(shù)
參數(shù)描述
MC56F8155 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-Bit Digital Signal Controllers
MC56F8155VFG 制造商:Rochester Electronics LLC 功能描述:16 BIT HYBRID CONTROLLER - Bulk
MC56F8155VFGE 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MC56F8156 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
MC56F8156VFV 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Freescale Semiconductor 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*