參數(shù)資料
型號： MC56F8157
廠商： Electronic Theatre Controls, Inc.
英文描述： 16-BIT HYBRID CONTROLLERS
中文描述： 16位混合控制器
文件頁數(shù)： 110/172頁
文件大小： 2444K
代理商： MC56F8157
56F8357 Technical Data, Rev. 8.0
110
Freescale Semiconductor
Preliminary
6.5.1.2
This bit reflects the current (non-clocked) state of the EMI_MODE pin. During reset, this bit, coupled with
the EXTBOOT signal, is used to initialize address bits [19:16] either as GPIO or as address. These settings
can be explicitly overwritten using the appropriate GPIO peripheral enable register at any time after reset.
In addition, this pin can be used as a general purpose input pin after reset.
EMI_MODE (EMI_MODE)—Bit 6
0 = External address bits [19:16] are initially programmed as GPIO
1 = When booted with EXTBOOT = 1, A[19:16] are initially programmed as address. If EXTBOOT is 0,
they are initialized as GPIO.
6.5.1.3
OnCE Enable (OnCE EBL)—Bit 5
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
6.5.1.4
This bit is always read as 0. Writing a 1 to this bit will cause the part to reset.
Software Reset (SW RST)—Bit 4
6.5.1.5
Stop Disable (STOP_DISABLE)—Bits 3–2
00 - Stop mode will be entered when the 56800E core executes a STOP instruction
01 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be
reprogrammed in the future
10 - The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then only be
changed by resetting the device
11 - Same operation as 10
6.5.1.6
Wait Disable (WAIT_DISABLE)—Bits 1–0
00 - Wait mode will be entered when the 56800E core executes a WAIT instruction
01 - The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can be
reprogrammed in the future
10 - The HawkV2 WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can then only
be changed by resetting the device
11 - Same operation as 10
6.5.2
Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A
reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this
register.
SIM Reset Status Register (SIM_RSTSTS)
Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)
Base + $1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
O
0
0
0
0
0
0
0
SWR
COPR
EXTR
POR
0
0
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
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