參數(shù)資料
型號: MC56F8157
廠商: Electronic Theatre Controls, Inc.
英文描述: 16-BIT HYBRID CONTROLLERS
中文描述: 16位混合控制器
文件頁數(shù): 27/172頁
文件大?。?/td> 2444K
代理商: MC56F8157
Signal Pins
56F8357 Technical Data, Rev. 8.0
Freescale Semiconductor
Preliminary
27
TXD1
(GPIOD6)
49
Output
Input/
Output
Tri-stated
Input
Transmit Data
— SCI1 transmit data output
Port D GPIO
— This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI output.
To deactivate the internal pull-up resistor, clear bit 6 in the
GPIOD_PUR register.
RXD1
(GPIOD7)
50
Input
Input/
Output
Input
Input
Receive Data
— SCI1 receive data input
Port D GPIO
— This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is SCI input.
To deactivate the internal pull-up resistor, clear bit 7 in the
GPIOD_PUR register.
TCK
137
Schmitt
Input
Input,
pulled low
internally
Test Clock Input
— This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pull-down resistor.
TMS
138
Schmitt
Input
Input,
pulled high
internally
Test Mode Select Input
— This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
TDI
139
Schmitt
Input
Input,
pulled high
internally
Test Data Input
— This input pin provides a serial input data
stream to the JTAG/EOnCE port. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
TDO
140
Output
Tri-stated
Test Data Output
— This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling
edge of TCK.
Table 2-2 Signal and Package Information for the 160-Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
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