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| 型號： | MC56F8255VLD |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 72/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | DSC 64K FLASH 60MHZ 44-LQFP |
| 標準包裝： | 160 |
| 系列： | 56F8xxx |
| 核心處理器： | 56800E |
| 芯體尺寸： | 16-位 |
| 速度： | 60MHz |
| 連通性： | CAN，I²C，LIN，SCI，SPI |
| 外圍設備： | LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 35 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 8x12b，D/A 1x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 44-LQFP |
| 包裝： | 管件 |
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MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Ordering Information
Freescale Semiconductor
74
Use the following list of considerations to assure correct operation of the MC56F825x/MC56F824x:
Provide a low-impedance path from the board power supply to each VDD pin on the MC56F825x/MC56F824x and
from the board ground to each VSS (GND) pin.
The minimum bypass requirement is to place 0.01–0.1 F capacitors positioned as near as possible to the package
supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs,
including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better tolerances.
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are
as short as possible.
Bypass the VDD and VSS with approximately 100 F, plus the number of 0.1 F ceramic capacitors.
PCB trace lengths should be minimal for high-frequency signals.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is
especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and
VSS circuits.
Take special care to minimize noise levels on the VREF, VDDA, and VSSA pins.
Using separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA is recommended.
Connect the separate analog and digital power and ground planes as near as possible to power supply outputs. If an
analog circuit and digital circuit are powered by the same power supply, you should connect a small inductor or ferrite
bead in serial with VDDA and VSSA traces.
Physically separate analog components from noisy digital components by ground planes. Do not place an analog trace
in parallel with digital traces. Place an analog ground trace around an analog signal trace to isolate it from digital traces.
Because the flash memory is programmed through the JTAG/EOnCE port, SPI, SCI, or I2C, the designer should
provide an interface to this port if in-circuit flash programming is desired.
If desired, connect an external RC circuit to the RESET pin. The resistor value should be in the range of 4.7 k
Ω to
10 k
Ω; the capacitor value should be in the range of 0.22 F to 4.7 F.
Configuring the RESET pin to GPIO output in normal operation in a high-noise environment may help to improve the
performance of noise transient immunity.
Add a 2.2 k
Ω external pullup on the TMS pin of the JTAG port to keep EOnCE in a restate during normal operation if
a JTAG converter is not present.
During reset and after reset but before I/O initialization, all I/O pins are at input state with internal pullup enabled. The
typical value of internal pullup is around 110 k
Ω. These internal pullups can be disabled by software.
To eliminate PCB trace impedance effect, each ADC input should have an RC filter of no less than 33 pF 10
Ω.
External clamp diodes on analog input pins are recommended.
9
Ordering Information
Table 46 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized
distributor to determine availability and to order devices.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC56F8256 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Digital Signal Controller Battery chargers and management |
| MC56F8256MLF | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSC 48 LQFP 64K FL RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| MC56F8256VLF | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSC 48 LQFP 64K FL RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| MC56F8257 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Digital Signal Controller Battery chargers and management |
| MC56F8257MLH | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSC 64 LQFP 64K FL RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
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