參數(shù)資料
型號： MC56F8347VVFE
廠商： Freescale Semiconductor
文件頁數(shù)： 108/172頁
文件大?。?/td> 0K
描述： IC DGTL SIGNAL CTLR 160-MAPBGA
標(biāo)準(zhǔn)包裝： 126
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 60MHz
連通性： CAN，EBI/EMI，SCI，SPI
外圍設(shè)備： POR，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 76
程序存儲器容量： 136KB（68K x 16）
程序存儲器類型： 閃存
RAM 容量： 6K x 16
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 外部
工作溫度： -40°C ~ 105°C
封裝/外殼： 160-BGA
包裝： 托盤
配用： MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8347 Technical Data, Rev.11
40
Freescale Semiconductor
Preliminary
3.2.3
External Clock Source
The recommended method of connecting an external clock is given in Figure 3-4. The external clock
source is connected to XTAL and the EXTAL pin is grounded. When using an external clock source, set
the OCCS_COHL bit high as well.
Figure 3-4 Connecting an External Clock Register
3.3 Registers
When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the
register definitions without the internal Relaxation Oscillator, since the 56F8347/56F8147 do NOT
contain this oscillator.
Part 4 Memory Map
4.1 Introduction
The 56F8347 and 56F8147 devices are 16-bit motor-control chips based on the 56800E core. These parts
use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip
RAM and Flash memories are used in both spaces.
This section provides memory maps for:
Program Address Space, including the Interrupt Vector Table
Data Address Space, including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for each device are summarized in Table 4-1. Flash memories’ restrictions are
identified in the “Use Restrictions” column of Table 4-1.
Note: Data Flash and Program RAM are NOT available on the 56F8147 device.
Table 4-1 Chip Memory Configurations
On-Chip Memory
56F8347
56F8147
Use Restrictions
Program Flash
128KB
Erase/Program via Flash interface unit and word writes to
CDBW
Data Flash
8KB
—
Erase/Program via Flash interface unit and word writes to
CDBW. Data Flash can be read via either CDBR or XDB2,
but not by both simultaneously
Program RAM
4KB
—
None
Data RAM
8KB
None
Program Boot Flash
8KB
Erase/Program via Flash Interface unit and word to CDBW
XTAL
EXTAL
External
VSS
Clock
Note: When using an external clocking source
with this configuration, the input “CLKMODE”
should be high and the COHL bit in the OSCTL
register should be set to 1.
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