參數(shù)資料
型號: MC56F8347VVFE
廠商: Freescale Semiconductor
文件頁數(shù): 94/172頁
文件大?。?/td> 0K
描述: IC DGTL SIGNAL CTLR 160-MAPBGA
標準包裝: 126
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 76
程序存儲器容量: 136KB(68K x 16)
程序存儲器類型: 閃存
RAM 容量: 6K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 105°C
封裝/外殼: 160-BGA
包裝: 托盤
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8347 Technical Data, Rev.11
28
Freescale Semiconductor
Preliminary
TRST
136
D9
Schmitt
Input
Input,
pulled
high
internally
Test Reset — As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete
hardware reset, TRST should be asserted whenever RESET
is asserted. The only exception occurs in a debugging
environment when a hardware device reset is required and
the JTAG/EOnCE module must not be reset. In this case,
assert RESET, but do not assert TRST.
To deactivate the internal pull-up resistor, set the JTAG bit in
the SIM_PUDR register.
Note:
For normal operation, connect TRST directly to VSS. If
the design is to be used in a debugging environment, TRST may be
tied to VSS through a 1K resistor.
PHASEA0
(TA0)
(GPIOC4)
155
A2
Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
Phase A — Quadrature Decoder 0, PHASEA input
TA0 — Timer A, Channel 0
Port C GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is PHASEA0.
To deactivate the internal pull-up resistor, clear bit 4 of the
GPIOC_PUR register.
PHASEB0
(TA1)
(GPIOC5)
156
B4
Schmitt
Input
Schmitt
Input/
Output
Schmitt
Input/
Output
Input,
pull-up
enabled
Phase B — Quadrature Decoder 0, PHASEB input
TA1 — Timer A, Channel
Port C GPIO — This GPIO pin can be individually
programmed as an input or output pin.
After reset, the default state is PHASEB0.
To deactivate the internal pull-up resistor, clear bit 5 of the
GPIOC_PUR register.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
Signal Name
Pin
No.
Ball
No.
Type
State
During
Reset
Signal Description
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