參數(shù)資料
型號: MC56F8357MPY60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 16-bit Digital Signal Processor
中文描述: 16-BIT, 240 MHz, OTHER DSP, PQFP160
封裝: 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-160
文件頁數(shù): 19/160頁
文件大?。?/td> 1394K
代理商: MC56F8357MPY60
56F8357 Signal Pins
56F8357 Technical Data
Preliminary
19
D7
(GPIOF0)
28
Input/
Output
Input/
Output
Tri-stated
Input
Data Bus
— D7 - D14 specify part of the data for external
program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), D7 - D15and EMI control signals are
tri-stated when the external bus is inactive.
Port F GPIO
— These eight GPIO pins can be individually
programmed as input or output pins.
At reset, these pins default to data bus functionality.
To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOF_PUR register.
Example: GPIOF0, clear bit 0 in the GPIOF_PUR register.
D8
(GPIOF1)
29
D9
(GPIOF2)
30
D10
(GPIOF3)
32
D11
(GPIOF4)
149
D12
(GPIOF5)
150
D13
(GPIOF6)
151
D14
(GPIOF7)
152
D15
(GPIOF8)
153
RD
52
Output
Tri-stated
Read Enable
— RD is asserted during external memory
read cycles. When RD is asserted low, pins D0 - D15
become inputs and an external device is enabled onto the
data bus. When RD is deasserted high, the external data is
latched inside the device. When RD is asserted, it qualifies
the A0 - A23, PS, DS, and CSn pins. RD can be connected
directly to the OE pin of a static RAM or ROM.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), RD is
tri-stated when the external bus
is inactive.
To deactivate the internal pull-up resistor, set the CTRL bit
in the SIM_PUDR register.
Table 2-2 56F8357 Signal and Package Information for the 160-Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關PDF資料
PDF描述
MC56F8357VPY60 16-bit Digital Signal Processor
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