參數(shù)資料
型號: MC56F8357MPY60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 16-bit Digital Signal Processor
中文描述: 16-BIT, 240 MHz, OTHER DSP, PQFP160
封裝: 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-160
文件頁數(shù): 37/160頁
文件大小: 1394K
代理商: MC56F8357MPY60
Interrupt Vector Table
56F8357 Technical Data
Preliminary
37
4.3 Interrupt Vector Table
Table 4-5
provides the reset and interrupt priority structure, including on-chip peripherals. The
table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the
table. The priority of an interrupt can be assigned to different levels, as indicated, allowing some
control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For
a selected priority level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA) register. Please
see
Section 5.6.11
for the reset value of the VBA.
In some configurations, the reset address and COP reset address will correspond to vector 0 and 1
of the interrupt vector table. In these instances, the first two locations in the vector table must
Table 4-4 Program Memory Map at Reset
Begin/End
Address
Mode 0 (MA = 0)
Mode 1
1
(MA = 1)
1.
If Flash Security Mode is enabled, EXTBOOT Mode 1 cannot be used. See
Security Features,
Part 7
.
Internal Boot
External Boot
Internal Boot
16-Bit External Address Bus
EMI_MODE = 0
2
,
3
16-Bit External Address Bus
2.
This mode provides maximum compatibility with 56F80x parts while operating externally.
3.
“EMI_MODE = 0” when EMI_MODE pin is tied to ground at boot up.
EMI_MODE = 1
4
20-Bit External Address Bus
4.
“EMI_MODE = 1” when EMI_MODE pin is tied to V
DD
at boot up.
Not accessible in reset configuration, since the address is above P:$00 FFFF. The higher bit address/GPIO (and/or chip
selects) pins must be reconfigured before this external memory is accessible.
P:$1F FFFF
P:$10 0000
External Program Memory
5
5.
External Program Memory
5
External Program Memory
6
6.
selects) pins must be reconfigured before this external memory is accessible.
Not accessible in reset configuration, since the address is above P:$0F FFFF. The higher bit address/GPIO (and/or chip
P:$0F FFFF
P:$03 0000
External Program Memory
COP Reset Address = 02 0002
7
Boot Location = 02 0000
7
7.
Booting from this external address allows prototyping of the internal Boot Flash.
P:$02 FFFF
P:$02 F800
On-Chip Program RAM
4KB
P:$02 F7FF
P:$02 2000
Reserved
116KB
P:$02 1FFF
P:$02 0000
Boot Flash
16KB
COP Reset Address = 02 0002
Boot Location = 02 0000
Boot Flash
16KB
(Not Used for Boot in this Mode)
P:$01 FFFF
P:$01 0000
Internal Program Flash
8
128KB
8.
have it’s own mass erase.
Two independent program flash blocks allow one to be programmed/erased while executing from another. Each block must
Internal Program Flash
128KB
P:$00 FFFF
P:$00 0000
Internal Program Flash
8
128KB
External Program RAM
COP Reset Address = 00 0002
Boot Location = 00 0000
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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