參數(shù)資料
型號： MC56F8357VPY60
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝： PLASTIC, LQFP-160
文件頁數(shù)： 97/177頁
文件大小： 4091K
代理商： MC56F8357VPY60
56F8357 Technical Data, Rev. 15
26
Freescale Semiconductor
Preliminary
WR
51
L4
Output
In reset,
output is
disabled,
pull-up is
enabled
Write Enable — WR is asserted during external memory write
cycles. When WR is asserted low, pins D0 - D15 become
outputs and the device puts data on the bus. When WR is
deasserted high, the external data is latched inside the
external device. When WR is asserted, it qualifies the A0 -
A23, PS, DS, and CSn pins. WR can be connected directly to
the WE pin of a static RAM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), WR is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in
the SIM_PUDR register.
PS
(CS0)
(GPIOD8)
53
N6
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Program Memory Select — This signal is actually CS0 in the
EMI, which is programmed at reset for compatibility with the
56F80x PS signal. PS is asserted low for external program
memory access.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), CS0 is tri-stated when the external bus is inactive.
CS0 resets to provide the PS function as defined on the
56F80x devices.
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOD_PUR register.
DS
(CS1)
(GPIOD9)
54
L5
Output
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Data Memory Select — This signal is actually CS1 in the EMI,
which is programmed at reset for compatibility with the 56F80x
DS signal. DS is asserted low for external data memory
access.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), CS1 is tri-stated when the external bus is inactive.
CS1 resets to provide the DS function as defined on the
56F80x devices.
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
To deactivate the internal pull-up resistor, clear bit 9 in the
GPIOD_PUR register.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
Signal
Name
Pin
No.
Ball No.
Type
State
During
Reset
Signal Description
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC56F8357,
MC56F8157
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC56F8357VPYE 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CNTRLR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MC56F8357VVF 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
MC56F8357VVFE 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CNTRLR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
MC56F8357VVFEJ 制造商:Freescale Semiconductor 功能描述:16 BIT HYBRID CONTROLLER - Bulk
MC56F8365 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
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