參數(shù)資料
型號(hào): MC68040
廠商: Motorola, Inc.
英文描述: Errata and Added Information to MC68360 Quad Integrated Communication Controller User Manual Rev 1
中文描述: 勘誤表和新增的資料MC68360四綜合通信控制器用戶手冊(cè)修訂1
文件頁(yè)數(shù): 12/28頁(yè)
文件大小: 159K
代理商: MC68040
12
MC68360 USER’S MANUAL ERRATA
MOTOROLA
17. Missing Note on Transmission on Demand.
One page 7-121, section 7.10.5, the following note should be added at the bottom of the
page:
The first bit of the frame will typically be clocked out 5-6 bit times after TOD has been set to
one.
18. Missing Last Step for SCC Initialization.
One page 7-129, section 7.10.9, add the following last step when initializing an SCC:
15. Setup buffer descriptors including control bits as required by the respective protocol ;
clear status bits by writing with zero.
19. Missing Note on Disable Receiver while Transmitting.
On page 7-158, the following note should be added after the description of DRT bit:
User should set the preamble bit in the transmit buffer descriptor if the QUICC is being
used in multi-drop UART mode.
Also on page 7-158, the following note should be added after the description of SYN
(Synchronous Mode) bit.
NOTE.
RINV bit in the GSMR must be cleared if synchronous UART
mode is selected.
20. Missing bits in HDLC mode register.
On page 7-178, the following bit definition was missing from the manual.
Bit 2 – BPM (HDLC BUS Priority Mode)
This bit determines the number of idle bits needed to be counted prior to a frame trans-
mission after a successful transmission.
0 = 10 bits
1 = 9 bits
Bit 1 – BCM (HDLC BUS Collision Sense Mode)
This bit determines the sample point of collision detection.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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