參數(shù)資料
型號: MC68040
廠商: Motorola, Inc.
英文描述: Errata and Added Information to MC68360 Quad Integrated Communication Controller User Manual Rev 1
中文描述: 勘誤表和新增的資料MC68360四綜合通信控制器用戶手冊修訂1
文件頁數(shù): 8/28頁
文件大?。?/td> 159K
代理商: MC68040
8
MC68360 USER’S MANUAL ERRATA
MOTOROLA
13. External MC040 type cycle (SRAM)
The following table should be placed after the table 6-11 on page 6-67.
14. Missing Note on Parity.
On page 6-71, section 6.13.3, the note below should be added after the note under the
definition of parity checking enable:
Parity is not supported with external assertion of DSACK or TA.
15. Error in note on CSNT40.
On page 6-72, the note on the top of the page states that SYNC bit must be set for CSNT40
function to take effect. This is not true. Regardless of the setting of SYNC bit CSNT40 will
take an effect.
16. Missing Statement on BACK40.
On page 6-72, the description of the BACK40, for the zero case, the following statement
should be added:
“The QUICC will assert TBI on an access to this memory area”.
17. Error in Note at TRLXQ.
On page 6-72, the 3rd note under TRLXQ-Timing Relax:
“User should avoid setting both TRLXQ and CSNTQ = 1, when TCYC = 0. This combination
will result in a bus cycle without CS assertion.” is not correct and should be removed.
18. Missing NOTE.
On page 6-74, bits 3 and 2 of the option register should have an asterisks. Also on the
bottom of the page the following note should be added.
External MC68040 Type bus
cycle Length
TSS40=0
2
3
4
5
6
7
8
TCYC =
TSS40=1
3
4
5
6
7
8
9
0
1
2
3
4
5
6
15
17
18
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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