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| 型號： | MC68040 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Errata and Added Information to MC68360 Quad Integrated Communication Controller User Manual Rev 1 |
| 中文描述： | 勘誤表和新增的資料MC68360四綜合通信控制器用戶手冊修訂1 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大小： | 159K |
| 代理商： | MC68040 |
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20
MC68360 USER’S MANUAL ERRATA
MOTOROLA
10. Typo on DRAM Page-Mode Page-Hit.
On page 10-31, Figure 10-23, address valid timing for the initial access is specification 6 not
6A.
Also on same figure the Specification 8 should be removed.
Also on the same figure Specification 106 was drawn to be referenced off of the rising edge
between S0 and S1. This is not correct. The correct reference clock edge is a rising edge
between S5 and S0.
11. Error in superscript.
On page 10-33, table 10-11, The superscript on specs 130, 132, 134, 135, 142 and 144
were not correct. Specs. 130 and 132 should have no superscripts at all. Specs 134 and 135
should have a superscript of 2 only. Specs 142, 143 and 144 should have a superscript of’
2’ instead of ‘3’.
12. Typo on BGACK/BB Negation Specification.
On page 10-33 and 10-49 there are two specifications for the negation of BGACK/BB.
Specification 139 and specification 238 are not correct neededand should be deleted. The
Figures affected are 10-25, 10-26 for 030/360 external masters and Figure 10-39 on page
10-50 for 040 external masters.
13. Error in Figure.
On pages 10-34, and 10-35, the negation timing for BCLRO is not correct. In both figures
the negation of the signal BCLRO is shown to be at the rising edge of CLKO1 where BGACK
is asserted. The signal is instead negated at the rising edge of CLKO1 where BGACK is
negated.
Also on same figures the negation delay between BR and BG, specification 136, should be
removed from the figures.
14. Missing Note on Bus Request Negation.
On pages 10-34 and 10-35, the following note should be added:
User should note that the negation timing of bus request from a slave QUICC pin may not
meet the required input specification for the QUICC in master mode. Because of this the
Num.
Characteristic
3.3 V or 5.0 V
25.0 MHz
Min
52.5
5.0V
Unit
33.34MHz
Min
40
Max
Max
115
R/W Low to CASx Asserted (Write)
ns
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68040FE25A | 功能描述:微處理器 - MPU 32B W/ CACHE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68040FE25V | 功能描述:微處理器 - MPU 32B W/ CACHE MMU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68040FE33A | 功能描述:微處理器 - MPU 32B W/ CACHE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68040FE33V | 功能描述:微處理器 - MPU 32B W/ CACHE MMU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68040FE40A | 功能描述:微處理器 - MPU 32B W/ CACHE MMU FPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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