參數(shù)資料
型號： MC68332ACFC16B1
廠商： Freescale Semiconductor
文件頁數(shù)： 26/88頁
文件大?。?/td> 0K
描述： IC MCU 32BIT 16MHZ 132-PQFP
標(biāo)準(zhǔn)包裝： 180
系列： M683xx
核心處理器： CPU32
芯體尺寸： 32-位
速度： 16MHz
連通性： EBI/EMI，SCI，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 15
程序存儲器類型： ROMless
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 132-BQFP 緩沖式
包裝： 托盤
MOTOROLA
MC68332
32
MC68332TS/D
CSPAR1 contains five 2-bit fields that determine the functions of corresponding chip-select pins.
CSPAR1[15:10] are not used. These bits always read zero; writes have no effect.
At reset, either the alternate function (01) or chip-select function (11) can be encoded. DATA pins are
driven to logic level one by a weak interval pull-up during reset. Encoding is for chip-select function un-
less a data line is held low during reset. Note that bus loading can overcome the weak pull-up and hold
pins low during reset. The following table shows the hierarchical selection method that determines the
reset functions of pins controlled by CSPAR1.
A pin programmed as a discrete output drives an external signal to the value specified in the port C
pin data register (PORTC), with the following exceptions:
1.
No discrete output function is available on pins BR, BG, or BGACK.
2.
ADDR23 provides E-clock output rather than a discrete output signal.
When a pin is programmed for discrete output or alternate function, internal chip-select logic still func-
tions and can be used to generate DSACK or AVEC internally on an address match.
Port size is determined when a pin is assigned as a chip select. When a pin is assigned to an 8-bit port,
the chip select is asserted at all addresses within the block range. If a pin is assigned to a 16-bit port,
the upper/lower byte field of the option register selects the byte with which the chip select is associated.
CSPAR1 —Chip Select Pin Assignment Register 1
$YFFA46
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CSPA1[4]
CSPA1[3]
CSPA1[2]
CSPA1[1]
CSPA1[0]
RESET:
0
DATA7
1
DATA
[7:6]
1
DATA
[7:5]
1
DATA
[7:4]
1
DATA
[7:3]
1
Table 14 CSPAR1 Pin Assignments
CSPAR0 Field
Chip Select Signal
Alternate Signal
Discrete Output
CSPA1[4]
CS10
ADDR23
ECLK
CSPA1[3]
CS9
ADDR22
PC6
CSPA1[2]
CS8
ADDR21
PC5
CSPA1[1]
CS7
ADDR20
PC4
CSPA1[0]
CS6
ADDR19
PC3
Table 15 Reset Pin Function of CS[10:6]
Data Bus Pins at Reset
Chip-Select/Address Bus Pin Function
DATA7
DATA6
DATA5
DATA4
DATA3
CS10/
ADDR23
CS9/
ADDR22
CS8/
ADDR21
CS7/
ADDR20
CS6/
ADDR19
11111
CS10
CS9
CS8
CS7
CS6
1111
0
CS10
CS9
CS8
CS7
ADDR19
111
0
X
CS10
CS9
CS8
ADDR20 ADDR19
11
0
X
CS10
CS9
ADDR21 ADDR20 ADDR19
1
0
X
CS10
ADDR22 ADDR21 ADDR20 ADDR19
0
XXXX
ADDR23 ADDR22 ADDR21 ADDR20 ADDR19
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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