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參數(shù)資料
| 型號： | MC68334GCEH20 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 25/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MICROPROCESSOR 20MHZ 132-PQFP |
| 標準包裝： | 36 |
| 系列： | M683xx |
| 核心處理器： | CPU32 |
| 芯體尺寸： | 32-位 |
| 速度： | 20MHz |
| 連通性： | EBI/EMI，UART/USART |
| 輸入/輸出數(shù)： | 47 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉換器： | A/D 8x8/10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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MC68334
MC68334TS/D REV. 1
31
Port size determines the way in which bus transfers to an external address are allocated. Port size of
eight bits or sixteen bits can be selected when a pin is assigned as a chip select. Port size and transfer
size affect how the chip-select signal is asserted. Refer to 3.5.4 Option Registers for more information.
Out of reset, chip-select pin function is determined by the logic level on a corresponding data bus pin.
These pins have weak internal pull-up drivers, but can be held low by external devices. Either 16-bit
chip-select function (%11) or alternate function (%01) can be selected during reset. All pins except the
boot ROM select pin (CSBOOT) are disabled out of reset. There are twelve chip-select functions and
only eight associated data bus pins. There is not a one-to-one correspondence. The table below shows
reset states.
The CSBOOT signal is normally enabled out of reset. The state of the DATA0 line during reset deter-
mines what port width CSBOOT uses. If DATA0 is held high (either by the weak internal pull-up driver
or by an external pull-up device), 16-bit width is selected. If DATA0 is held low, 8-bit port size is selected.
A pin programmed as a discrete output drives an external signal to the value specified in the pin data
register. No discrete output function is available on pins CSBOOT, BR, BG, or BGACK. ADDR23 pro-
vides ECLK output rather than a discrete output signal.
When a pin is programmed for discrete output or alternate function, internal chip-select logic still func-
tions and can be used to generate DSACK or AVEC internally on an address and control signal match.
3.5.3 Base Address Registers
Each chip select has an associated base address register. A base address is the lowest address in the
block of addresses enabled by a chip select. Block size is the extent of the address block above the
base address. Block size is determined by the value contained in a BLKSZ field. Block addresses for
different chip selects can overlap.
The BLKSZ field determines which bits in the base address field are compared to corresponding bits on
the address bus during an access. Provided other constraints determined by option register fields are
also satisfied, when a match occurs, the associated chip-select signal is asserted.
The chip-select address compare logic uses only the most significant bits to match an address within a
block. The value of the base address must be a multiple of block size. Base address register diagrams
show how base register bits correspond to address lines.
After reset, the MCU fetches the initialization routine from the address contained in the reset vector, lo-
cated beginning at address $000000 of program space. To support bootstrap operation from reset, the
base address field in chip-select base address register boot (CSBARBT) has a reset value of all zeros.
A memory device containing the reset vector and initialization routine can be automatically enabled by
CSBOOT after a reset. The block size field in CSBARBT has a reset value of 512 Kbytes.
Table 18 Reset Pin Function of CS[10:6]
Data Bus Pins at Reset
Chip-Select/Address Bus Pin Function
DATA7
DATA6
DATA5
DATA4
DATA3
CS10/
ADDR23
CS9/
ADDR22
CS8/
ADDR21
CS7/
ADDR20
CS6/
ADDR19
11111
CS10
CS9
CS8
CS7
CS6
1111
0
CS10
CS9
CS8
CS7
ADDR19
111
0
X
CS10
CS9
CS8
ADDR20 ADDR19
11
0
X
CS10
CS9
ADDR21 ADDR20 ADDR19
1
0
X
CS10
ADDR22 ADDR21 ADDR20 ADDR19
0
XXXX
ADDR23 ADDR22 ADDR21 ADDR20 ADDR19
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