參數(shù)資料
型號(hào)： MC68334GCEH20
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 49/76頁(yè)
文件大?。?/td> 0K
描述： IC MICROPROCESSOR 20MHZ 132-PQFP
標(biāo)準(zhǔn)包裝： 36
系列： M683xx
核心處理器： CPU32
芯體尺寸： 32-位
速度： 20MHz
連通性： EBI/EMI，UART/USART
輸入/輸出數(shù)： 47
程序存儲(chǔ)器類(lèi)型： ROMless
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8/10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 132-BQFP 緩沖式
包裝： 托盤(pán)
MC68334
MC68334TS/D REV. 1
53
5.3.3 Scheduler
When a service request is received, the scheduler determines which TPU channel is serviced by the
microengine. A channel can request service for one of four reasons: for host service, for a link to another
channel, for a match event, or for a capture event. The host system assigns each active channel one
of three priorities: high, middle, or low. When multiple service requests are received simultaneously, a
priority-scheduling mechanism grants service based on channel number and assigned priority.
5.3.4 Microengine
The microengine is composed of a control store and an execution unit. Control-store ROM holds the
microcode for each factory-masked time function. When assigned to a channel by the scheduler, the
execution unit executes microcode for a function assigned to that channel by the host CPU. Microcode
can also be executed from the TPURAM module instead of the control store. The TPURAM module al-
lows emulation and development of custom TPU microcode without the generation of a microcode ROM
mask. Refer to 5.5 Emulation Support for more information.
5.3.5 Host Interface
Host interface registers allow communication between the host CPU and the TPU, both before and dur-
ing execution of a time function. The registers are accessible from the IMB through the TPU bus inter-
face unit.
5.3.6 Parameter RAM
Parameter RAM occupies 256 bytes at the top of the system address map. Channel parameters are
organized as 128 16-bit words. Although all parameter word locations in RAM can be accessed by all
channels, only 100 are normally used: channels 0 to 13 use six parameter words, while channels 14
and 15 each use eight parameter words. The parameter RAM address map shows how parameter
words are organized in memory.
The host CPU specifies function parameters by writing the appropriate RAM address. The TPU reads
the RAM to determine channel operation. The TPU can also store information to be read by the CPU in
RAM. Detailed descriptions of the parameters required by each time function are beyond the scope of
this technical summary. Refer to the
TPU Reference Manual (TPURM/AD) for more information.
For pre-programmed functions, one of the parameter words associated with each channel contains
three channel control fields. These fields perform the following functions:
PSC — Forces the output level of the pin.
PAC — For input capture, PAC specifies the edge transition to be detected. For output comparison,
PAC specifies the logic level to be output when a match occurs.
TBS — Specifies channel direction (input or output) and assigns a time base to the input capture
and output compare functions of the channel.
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