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| 型號： | MC68334GCFC16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 51/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 16MHZ 1K RAM 132-PQFP |
| 標準包裝： | 36 |
| 系列： | M683xx |
| 核心處理器： | CPU32 |
| 芯體尺寸： | 32-位 |
| 速度： | 16MHz |
| 連通性： | EBI/EMI，UART/USART |
| 輸入/輸出數(shù)： | 47 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉換器： | A/D 8x8/10b |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
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MC68334
MC68334TS/D REV. 1
55
5.4.3 Interchannel Communication
The autonomy of the TPU is enhanced by the ability of a channel to affect the operation of one or more
other channels without CPU intervention. Interchannel communication can be accomplished by issuing
a link service request to another channel, by controlling another channel directly, or by accessing the
parameter RAM of another channel.
5.4.4 Programmable Channel Service Priority
The TPU provides a programmable service priority level to each channel. Three priority levels are avail-
able. When more than one channel of a given priority requests service at the same time, arbitration is
accomplished according to channel number. To prevent a single high-priority channel from permanently
blocking other functions, other service requests of the same priority are performed in channel order after
the lowest-numbered, highest-priority channel is serviced.
5.4.5 Coherency
For data to be coherent, all available portions of it must be identical in age, or must be logically related.
As an example, consider a 32-bit counter value that is read and written as two 16-bit words. The 32-bit
value is read-coherent only if both 16-bit portions are updated at the same time, and write-coherent only
if both portions take effect at the same time. Parameter RAM hardware supports coherent access of two
adjacent 16-bit parameters. The host CPU must use a long-word operation to guarantee coherency.
5.5 Emulation Support
Although factory-programmed time functions can perform a wide variety of control tasks, they may not
be ideal for all applications. The TPU provides emulation capability that allows the user to develop new
time functions. Emulation mode is entered by setting the EMU bit in the TPUMCR. In emulation mode,
an auxiliary bus connection is made between TPURAM and the TPU module, and access to TPURAM
via the intermodule bus is disabled. A 9-bit address bus, a 32-bit data bus, and control lines transfer
information between the modules. To ensure exact emulation, RAM module access timing remains con-
sistent with access timing of the TPU ROM control store.
To support changing TPU application requirements, Freescale has established a TPU function library.
The function library is a collection of TPU functions written for easy assembly in combination with each
other or with custom functions. Refer to Freescale Programming Note TPUPN00/D,
Using the TPU Func-
tion Library and TPU Emulation Mode for information about developing custom functions and accessing
the TPU function library. Refer to the
TPU Reference Manual (TPURM/AD) for more information about
specific functions.
5.6 Time Functions
The following paragraphs describe factory-programmed time functions implemented in the TPU micro-
code ROM. A complete description of the functions is beyond the scope of this summary. Refer to the
TPU Reference Manual (TPURM/AD) for additional information.
5.6.1 Table Stepper Motor (TSM)
The TSM function provides for acceleration and deceleration control of a stepper motor with a program-
mable number of step rates up to 58. TSM uses a table in parameter RAM, rather than an algorithm, to
define the stepper motor acceleration profile, allowing the user to fully define the profile. In addition, a
slew rate parameter allows fine control of the terminal running speed of the motor independent of the
acceleration table. The CPU need only write a desired position, and the TPU accelerates, slews, and
decelerates the motor to the required position. Full and half step support is provided for two-phase mo-
tors. In addition, a slew rate parameter allows fine control of the terminal running speed of the motor
independent of the acceleration table.
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