參數(shù)資料
型號(hào)： MC68334GCFC16
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 71/76頁(yè)
文件大小： 0K
描述： IC MCU 16MHZ 1K RAM 132-PQFP
標(biāo)準(zhǔn)包裝： 36
系列： M683xx
核心處理器： CPU32
芯體尺寸： 32-位
速度： 16MHz
連通性： EBI/EMI，UART/USART
輸入/輸出數(shù)： 47
程序存儲(chǔ)器類型： ROMless
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8/10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 132-BQFP 緩沖式
包裝： 托盤
MC68334
MC68334TS/D REV. 1
73
STOP — Stop Control
0 = TPURAM array operates normally.
1 = TPURAM array enters low-power stop mode.
This bit controls whether the TPURAM array is in stop mode or normal operation. Reset state is zero,
for normal operation. In stop mode, the array retains its contents, but cannot be read or written by the
CPU.
RASP — RAM Array Space Field
0 = TPURAM array is placed in unrestricted space
1 = TPURAM array is placed in supervisor space
TRAMTST
— TPURAM Test Register
$YFFB02
TRAMTST is used for factory testing of the TPURAM module.
ADDR[23:11] — RAM Array Base Address
This field specifies ADDR[23:11] of the TPURAM array base address when the array is enabled.
ADDR11 determines the 2-Kbyte boundary that the block of addresses containing the array is mapped
to. The array occupies only the upper 1024 bytes of the 2-Kbyte block of addresses. When ADDR11 bit
is set, valid array addresses range from $0C00 to%0FFFF; when the ADDR11 bit is cleared, valid array
addresses range from $0400 to $07FF.
RAMDS — RAM Array Disable
0 = TPURAM array is enabled
1 = TPURAM array is disabled
The TPURAM array is disabled by internal logic after a master reset. Writing a valid base address to
the TPURAM array base address field (bits [15:3]) automatically clears RAMDS, enabling the TPURAM
array.
7.4 TPURAM Operation
There are six TPURAM operating modes, as follows:
The TPURAM module is in normal mode when powered by VDD. The array can be accessed by
byte, word, or long word. A byte or aligned word (high-order byte is at an even address) access
only takes one bus cycle or two system clocks. A long word or misaligned word access requires
two bus cycles.
Standby mode is intended to preserve TPURAM contents when VDD is removed. TPURAM con-
tents are maintained by VSTBY. Circuitry within the TPURAM module switches to the higher of
VDD or VSTBY with no loss of data. When TPURAM is powered by VSTBY, access to the array is
not guaranteed.
Reset mode allows the CPU to complete the current bus cycle before resetting. When a synchro-
nous reset occurs while a byte or word TPURAM access is in progress, the access will be com-
pleted. If reset occurs during the first word access of a long-word operation, only the first word
access will be completed. If reset occurs during the second word access of a long word operation,
the entire access will be completed. Data being read from or written to the RAM may be corrupted
by asynchronous reset.
TRAMBAR
— TPURAM Base Address and Status Register
$YFFB04
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
NOT USED
RAMD
S
RESET:
0
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