MOTOROLA
MC68336/376
xvi
USER’S MANUAL
(Continued)
Paragraph
Title
Page
TABLE OF CONTENTS
D.8
Time Processor Unit (TPU) .................................................................... D-73
D.8.1
TPU Module Configuration Register ............................................... D-73
D.8.2
Test Configuration Register ............................................................ D-75
D.8.3
Development Support Control Register .......................................... D-75
D.8.4
Development Support Status Register ........................................... D-76
D.8.5
TPU Interrupt Configuration Register ............................................. D-77
D.8.6
Channel Interrupt Enable Register ................................................. D-77
D.8.7
Channel Function Select Registers ................................................ D-78
D.8.8
Host Sequence Registers ............................................................... D-78
D.8.9
Host Service Request Registers .................................................... D-79
D.8.10
Channel Priority Registers .............................................................. D-79
D.8.11
Channel Interrupt Status Register .................................................. D-80
D.8.12
Link Register .................................................................................. D-80
D.8.13
Service Grant Latch Register ......................................................... D-80
D.8.14
Decoded Channel Number Register .............................................. D-80
D.8.15
TPU Parameter RAM ..................................................................... D-80
D.9
Standby RAM Module with TPU Emulation Capability (TPURAM) ........ D-82
D.9.1
TPURAM Module Configuration Register ....................................... D-82
D.9.2
TPURAM Test Register .................................................................. D-82
D.9.3
TPURAM Module Configuration Register ....................................... D-82
D.10
TouCAN Module ..................................................................................... D-84
D.10.1
TouCAN Module Configuration Register ........................................ D-85
D.10.2
TouCAN Test Configuration Register ............................................. D-88
D.10.3
TouCAN Interrupt Configuration Register ...................................... D-88
D.10.4
Control Register 0 .......................................................................... D-88
D.10.5
Control Register 1 .......................................................................... D-90
D.10.6
Prescaler Divide Register ............................................................... D-91
D.10.7
Control Register 2 .......................................................................... D-91
D.10.8
Free Running Timer ....................................................................... D-92
D.10.9
Receive Global Mask Registers ..................................................... D-93
D.10.10
Receive Buffer 14 Mask Registers ................................................. D-93
D.10.11
Receive Buffer 15 Mask Registers ................................................. D-93
D.10.12
Error and Status Register ............................................................... D-94
D.10.13
Interrupt Mask Register .................................................................. D-96
D.10.14
Interrupt Flag Register .................................................................... D-96
D.10.15
Error Counters ................................................................................ D-97
336376UMBook Page xvi Friday, November 15, 1996 2:09 PM