MOTOROLA
MC68336/376
xviii
USER’S MANUAL
(Continued)
Figure
Title
Page
LIST OF ILLUSTRATIONS
8-1
QADC Block Diagram ..................................................................................... 8-1
8-2
QADC Input and Output Signals .................................................................... 8-3
8-3
Example of External Multiplexing ................................................................. 8-11
8-4
QADC Module Block Diagram ...................................................................... 8-13
8-5
Conversion Timing ....................................................................................... 8-14
8-6
Bypass Mode Conversion Timing ................................................................. 8-15
8-7
QADC Queue Operation with Pause ............................................................ 8-18
8-8
QADC Clock Subsystem Functions .............................................................. 8-24
8-9
QADC Clock Programmability Examples ..................................................... 8-26
8-10
QADC Conversion Queue Operation ........................................................... 8-29
8-11
QADC Interrupt Vector Format ..................................................................... 8-33
9-1
QSM Block Diagram ....................................................................................... 9-1
9-2
QSPI Block Diagram ...................................................................................... 9-5
9-3
QSPI RAM ...................................................................................................... 9-7
9-4
Flowchart of QSPI Initialization Operation .................................................... 9-10
9-5
Flowchart of QSPI Master Operation (Part 1) .............................................. 9-11
9-6
Flowchart of QSPI Master Operation (Part 2) .............................................. 9-12
9-7
Flowchart of QSPI Master Operation (Part 3) .............................................. 9-13
9-8
Flowchart of QSPI Slave Operation (Part 1) ................................................ 9-14
9-9
Flowchart of QSPI Slave Operation (Part 2) ................................................ 9-15
9-10
SCI Transmitter Block Diagram .................................................................... 9-22
9-11
SCI Receiver Block Diagram ........................................................................ 9-23
10-1
CTM4 Block Diagram ................................................................................... 10-1
10-2
CPSM Block Diagram ................................................................................... 10-4
10-3
FCSM Block Diagram ................................................................................... 10-5
10-4
MCSM Block Diagram .................................................................................. 10-8
10-5
DASM Block Diagram ................................................................................. 10-11
10-6
Pulse-Width Modulation Submodule Block Diagram .................................. 10-13
11-1
TPU Block Diagram ...................................................................................... 11-1
11-2
TCR1 Prescaler Control ............................................................................. 11-14
11-3
TCR2 Prescaler Control ............................................................................. 11-14
13-1
TouCAN Block Diagram ............................................................................... 13-1
13-2
Typical CAN Network ................................................................................... 13-2
13-3
Extended ID Message Buffer Structure ........................................................ 13-3
13-4
Standard ID Message Buffer Structure ........................................................ 13-4
13-5
TouCAN Interrupt Vector Generation ......................................................... 13-19
A-1
CLKOUT Output Timing Diagram ................................................................. A-10
A-2
External Clock Input Timing Diagram ........................................................... A-10
A-3
ECLK Output Timing Diagram ...................................................................... A-10
A-4
Read Cycle Timing Diagram ........................................................................ A-11
A-5
Write Cycle Timing Diagram ......................................................................... A-12
336376UMBook Page xviii Friday, November 15, 1996 2:09 PM