MC68F375
CDR MoneT FLASH FOR THE IMB3 (CMFI)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
10-6
nal to externally control program or erase operations to array block 0 (EPEB0). Three
other pins: VSSF VDD3F and VPP provide power to the module.
10.2.1 External Interface
The CMFI EEPROM module uses external signals to provide some external control of
operations and provide power. These signals are listed in Table 10-1.
Table 10-1 CMFI EEPROM Module External Signals
Description
MNEMONIC
Comments
Internal mem-
ory patch sig-
nals
INTPATCHB
These signals signify that the current bus cycle will be provided by the internal
patch memory instead of the CMFI.
The CMFI EEPROM BIU will force an aborted access to the CMFI if any of the
four patch signals = “1” to remain synchronized with the IMB3.
Thus the CMFI will not assert the data, data transfer acknowledge or burst trans-
fer acknowledge if any of the internal memory patch signals = “1”.
Master pro-
gram and
erase enable
EPEE
This optional signal externally controls program or erase operation. To enable
these operations the signal should be at the logic "1” level, while a logic "0” level
disables these operations in the CMFI module. The EPEE signal includes a pull
down device to keep a logic "0” unless the pin is driven to a logic "1” and a digital
filter to protect from external noise. On the MC68F375, this signal is connected to
VDD to allow program and erase operations at all times.
Block 0 pro-
gram and
erase enable
EPEB0
This optional signal will externally control program or erase operations to array
block 0. To enable these operations the signal should be at the logic “1” level,
while a logic “0” level disables these operations in the CMFI Module. This signal
may be generated by any desired method and must remain valid throughout the
program or erase software starting their respective operation. The EPEB0 pin will
include a pull down device to keep a logic “0” unless the pin is driven to a logic
"1” and a digital filter to protect from external noise. When not connected to EPEB0
this signal will be connected to VDD to allow program and erase operations.
CMFI ground
VSSF
To reduce noise in the read path no other circuits should be connected to the
CMFI VSSF supply. A maximum of 2 CMFI Modules may be connected to a VSSF
supply pin. This VSSF pin must be isolated from all other VSS pins inside the de-
vice.
CMFI power
supply
VDDF
To reduce noise in the read path no other circuits should be connected to the
CMFI VDDF supply pin. A maximum of 2 CMFI Modules may be connected to a
VDDF supply pin. This VDDF pin must be isolated from all other VDD pins inside the
device. The specified voltage range during operation is 3. 0 V to 3. 6 V.
Program and
erase high
voltage supply
VPP
VPP provides the high voltage (4. 75 V to 5. 25 V) used during program and erase
operations of the CMFI Module. A maximum of 2 CMFI Modules may be connect-
ed to a VPP supply pin. The suggested voltage at the VPP pin should be equal to
the VDD voltage during all operations except program and erase.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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