參數(shù)資料
型號(hào)： MC68HC05E5P
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封裝： PLASTIC, DIP-28
文件頁數(shù)： 104/140頁
文件大?。?/td> 847K
代理商： MC68HC05E5P
NON-DISCLOSURE
AGREEMENT
REQUIRED
Computer Operating Properly (COP) Watchdog
General Release Specification
MC68HC05E5 — Rev. 1.0
66
Computer Operating Properly (COP) Watchdog
MOTOROLA
10.3 System Control and Status Register
The SCSR is a read/write register containing the control flags for the
COP rate, COP inhibit, and IRQ level and status flags indicating the
cause of the last reset. Figure 10-1 shows the value of each bit in the
SCSR when coming out of reset.
NOTE:
The debounce time for the IRQ input must be shorter than the COP
timeout period.
STOPR — Illegal STOP Instruction Reset
STOPR is a read-only status bit. This bit is set by the execution of a
STOP instruction when the STOP instruction option is disabled. This
bit is cleared by POR, external reset, or COP reset.
1 = Last reset was the execution of a disabled STOP instruction.
0 = Last reset was not the execution of a disabled STOP
instruction.
ILADR — Illegal Address Reset
ILADR is a read-only status bit. This bit is set by an ILADR reset, but
is cleared by POR, external reset, or COP reset.
1 = Last reset was an ILADR reset.
0 = Last reset was not an ILADR reset.
Address:
$0013
Bit 7
654321
Bit 0
Read:
0
STOPR
ILADR
COPR
CRS1
CRS0
Write:
Reset:
0
R
0
R = Determined by cause of previous reset
Figure 10-1. System Control and Status Register (SCSR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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