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參數(shù)資料
| 型號： | MC68HC05E5P |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 4/140頁 |
| 文件大?。?/td> | 847K |
| 代理商： | MC68HC05E5P |
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Synchronous Serial Interface (SSI)
SSI Registers
MC68HC05E5 — Rev. 1.0
General Release Specification
MOTOROLA
Synchronous Serial Interface (SSI)
101
NON-DISCLOSURE
AGREEMENT
REQUIRED
12.4.2 SSI Status Register
The SSI status register (SSR) is located at address $000B and contains
three bits.
SF — SSI Flag
This bit is set upon occurrence of the last rising clock edge and
indicates that a data transfer has taken place. It has no effect on any
further transmissions and can be ignored without problem. However,
SF must be cleared before a master can initiate a transfer. SF is
cleared by reading the SSR with SF set followed by a read or write of
the serial data register. If it is cleared before the last edge of the next
byte, it will be set again. Reset clears this bit.
DCOL — Data Collision
This is a read-only status bit which indicates that an invalid access to
the data register has been made. This can occur any time after the
first falling edge of SCK and before SF is set. DCOL is cleared by
reading the status register with SF set followed by a read or write of
the data register. If the last part of the clearing sequence is done after
another transmission has been started, DCOL will be set again. Reset
also clears this bit.
TIPL
The state of the PB3 pin is latched and placed into this bit on the
eighth rising SCK clock during a shift operation. This is the case
regardless of the state of MSTR and CPOL in the SSI control register.
Reset clears this bit.
Address:
$000B
Bit 7
654321
Bit 0
Read:
SF
DCOL
00000
TIPL
Write:
Reset:
00001000
= Unimplemented
Figure 12-5. SSI Status Register (SSR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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