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  • 參數(shù)資料
    型號: MC68HC05E6MFB
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44
    封裝: PLASTIC, QFP-44
    文件頁數(shù): 114/140頁
    文件大?。?/td> 1584K
    代理商: MC68HC05E6MFB
    Resets and Interrupts
    Interrupts
    MC68HC05E6 — Rev. 1.0
    Resets and Interrupts
    If the COP watchdog timer is allowed to timeout, an internal reset is
    generated to reset the MCU. Because the internal reset signal is used,
    the MCU comes out of a COP reset in the same operating mode it was
    in when the COP timeout was generated.
    The COP reset function is enabled or disabled by a mask option on the
    MC68HC05E6 or by the COP bit in the LVIOPT register on the
    MC68HC705E6 (see Mask options).
    Illegal address
    reset
    When an opcode fetch occurs from an address which is not part of the
    RAM ($0080–$00FF), ROM/
    EPROM ($0800–$1FFF)/($0700–$1FFF)
    or EEPROM ($0100–$019F), the device is automatically reset.
    NOTE:
    No RTS or RTI instruction should be placed at the end of a memory
    block, i.e. at address $017F, since this would result in an illegal address
    reset.
    Interrupts
    The MCU can be interrupted by six different sources (five maskable
    hardware interrupts and one nonmaskable software interrupt):
    External signal on the IRQ pin
    Core timer interrupt
    Low voltage indication interrupt (LVI)
    16-bit programmable timer interrupt
    Keyboard interrupt
    Software interrupt instruction (SWI)
    Interrupts cause the processor to save the register contents on the stack
    and to set the interrupt mask (I-bit) to prevent additional interrupts. The
    RTI instruction (ReTurn from Interrupt) causes the register contents to
    be recovered from the stack and normal processing to resume. While
    executing the RTI instruction, the interrupt mask bit (I-bit) will be cleared
    3-resets
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    Freescale Semiconductor, Inc.
    For More Information On This Product,
    Go to: www.freescale.com
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