參數(shù)資料
型號(hào): MC68HC05E6VFB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 117/140頁
文件大?。?/td> 1141K
代理商: MC68HC05E6VFB
Resets and Interrupts
MC68HC05E6 — Rev. 1.0
78
Resets and Interrupts
MOTOROLA
Nonmaskable software interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a
nonmaskable interrupt: it is executed regardless of the state of the I-bit
in the CCR. If the I-bit is zero (interrupts enabled), SWI is executed after
interrupts that were pending when the SWI was fetched, but before
interrupts generated after the SWI was fetched. The SWI interrupt
service routine address is specified by the contents of memory locations
$1FFC and $1FFD.
Maskable hardware interrupts
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts
(internal and external) are masked. Clearing the I-bit allows interrupt
processing to occur.
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse could be latched
and serviced as soon as the I-bit is cleared.
External interrupt
(IRQ)
This external interrupt source will vector to the start address contained
in memory locations $1FFA and $1FFB. IRQ can be selected to be either
edge sensitive or edge-and-level sensitive (see Mask options) by the
IRQ bit in the LVIOPT register.
Core timer
interrupts
There are two core timer interrupt flags that cause an interrupt whenever
an interrupt is enabled and its flag becomes set (RTIF and CTOF). The
interrupt flags and enable bits are located in the core timer control and
status register (CTCSR). These interrupts vector to the same interrupt
service routine, whose start address is contained in memory locations
$1FF8 and $1FF9. Full details of the core timer can be found in Core
To make use of the real time interrupt, the RTIE bit must first be set. The
RTIF bit will then be set after the specified number of counts.
6-resets
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