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參數(shù)資料
| 型號： | MC68HC05E6VFB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 73/140頁 |
| 文件大?。?/td> | 1141K |
| 代理商： | MC68HC05E6VFB |
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Input/Output Ports
MC68HC05E6 — Rev. 1.0
38
Input/Output Ports
MOTOROLA
port C registers are cleared, thereby returning the port pins to normal
inputs with pull-up resistors.
NOTE:
Due to an internal clamp diode, the pins cannot be pulled higher than
VDD, even when configured as open-drain outputs, that is, maximum
ratings for input voltage still apply to open drain outputs.
When configured as input pins, port C bits 0–7 provide a wired-OR
keyboard interrupt facility and will generate an interrupt, provided the
keyboard interrupt enable bit (KIE) in the keyboard/timer register
(KEY/TIM) is set. When configured as inputs with keyboard interrupt
capability, the pins can also have pull-ups connected to them by
correctly configuring the DDRC and CONFC bits as outlined in Table 5.
The structure of the port C pins is shown diagrammatically in Figure 9.
Once a high to low transition is sensed on any of the port C lines
(PC0–PC7) configured as inputs and not being used by the timer, a
keyboard interrupt will be generated and the keyboard status flag will be
set, provided the interrupt mask bit of the condition code register is
cleared and KIE is set. The interrupt service routine is specified by the
contents of the memory locations $1FF2 and $1FF3. The interrupt is
cleared by writing a ‘1’ to the KIRST bit in the KEY/TIM register. The
keyboard interrupt is negative edge-and-level sensitive and will force the
processor out of STOP or WAIT mode.
Table 5 Port C I/O pin congurations
DDRC CONFC
Function
0
Input with pull-up
0
1
Input without pull-up
1
0
Push-pull output
1
Open-drain output
4-ports
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