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參數(shù)資料
| 型號： | MC68HC05E6VFB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 96/140頁 |
| 文件大?。?/td> | 1141K |
| 代理商： | MC68HC05E6VFB |
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Programmable Timer
Timer functions
MC68HC05E6 — Rev. 1.0
MOTOROLA
Programmable Timer
59
9-ptimer
Output compare
high register,
Output compare
low register
The 16-bit output compare register is made up of two 8-bit registers at
locations $16 (MSB) and $17 (LSB). The contents of the output compare
register are continually compared with the contents of the free-running
counter and, if a match is found, the output compare flag (OCF) in the
timer status register is set and the output level (OLV) bit clocked to the
output level register. The output compare register values and the output
level bit should be changed after each successful comparison to
establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable
bit (OCIE) is set. (The free-running counter is updated every four internal
bus clock cycles.)
After a processor write cycle to the output compare register containing
the MSB ($16), the output compare function is inhibited until the LSB
($17) is also written. The user must write both bytes (locations) if the
MSB is written first. A write made only to the LSB will not inhibit the
compare function. The processor can write to either byte of the output
compare register without affecting the other byte. The output level (OLV)
bit is clocked to the output level register whether the output compare flag
(OCF) is set or clear. The minimum time required to update the output
compare register is a function of the program rather than the internal
hardware. Because the output compare flag and the output compare
register are not defined at power on, and are not affected by reset, care
must be taken when initialising output compare functions with software.
The following procedure is recommended:
1. write to output compare high to inhibit further compares,
2. read the timer status register to clear OCF (if set,
3. write to output compare low to enable the output compare
function.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Output compare high (OCH)
$0016 (bit 15)
(bit 8) Undened
Output compare low (OCL)
$0017
Undened
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05F32 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
| MC68HC05F32CFU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
| MC68HC05F32CPU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
| MC68HC05F32FU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
| MC68HC05F32PU | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:a member of the M68HC05 family of HCMOS |
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