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| 型號(hào)： | MC68HC05F8B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1.8 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | PLASTIC, SDIP-56 |
| 文件頁(yè)數(shù)： | 98/126頁(yè) |
| 文件大?。?/td> | 1084K |
| 代理商： | MC68HC05F8B |
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MC68HC05F8
MOTOROLA
8-3
MANCHESTER ENCODER/DECODER
8
8.2.1.1
Idle State of Encoder
Upon reset the encoder enable bit (NCE) is cleared, ENCOOUT pin is at high impedance, internal
encoding clock is inhibited, and the encoder is in the idle state. The encode data register empty
ag (NCM) and the encoding completion ag (NCC) in the status register are both set.
8.2.1.2
Initialization of Encoder
The encoder is initialized by conguring the bit rate control bits (BR0, BS1) and setting NCE=1 to
place the encoder in the standby state. The encoding process is initiated by writing to the Encoder
Data register, which is then transferred to the encode data shift register ready for encoding. After
2 delay bits (ENCOOUT pin is low) and 2 sync bits, the encoded data is shifted out to the
ENCOOUT pin, LSB rst. See Figure 8-3 for a graphical representation.
8.2.1.3
Encode Data Register Empty Flag (NCM)
and Encode Interrupt
After the last data bit in the encode data shift register is encoded and output to ENCOOUT, a
trailing bit followed by two pause bits are generated to conclude a one byte transmission. After
this, if the Encode Data register is not empty, the encoding process is repeated.
When data from the encode data register is transferred to the encode data shift register, the
encoder data register empty ag (NCM) is set, causing an interrupt to be generated if the encode
interrupt is enabled (i.e. NIE = 1). The next byte of data to be encoded can be written in to the
encoder data register in an interrupt service routine. The NCM bit is automatically cleared by
writing to the encode data register after accessing the MANCD Status register.
8.2.1.4
End Pattern Generation and Next Data Byte Encoding
The end pattern of one byte sequence is generated automatically after the last bit. This pattern
consists of a trailing bit and two pause bits. After this, if the Encode Data register is empty,
ENCOOUT is set to high impedance, and the encoder returns to the standby state. The encoding
complete ag (NCC) will be set, and an interrupt is generated if the encoding complete interrupt
enable bit (CIE) is set. If the encode data register is not empty, the next encoding is started.
8.2.1.5
Disable Encoder
The encoder is disabled by setting NCE=0; causing the ENCOOUT pin to be tri-stated. If the NCE
bit is cleared while an encoding is in progress (indicated by NCC=0), the encoder will complete
encoding of the current byte, plus the end patterns, before going into idle.
TPG
71
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