參數(shù)資料
型號: MC68HC05J3CDW
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝: SOIC-20
文件頁數(shù): 30/74頁
文件大小: 814K
代理商: MC68HC05J3CDW
MOTOROLA
5-2
MC68HC05J3
CORE TIMER
5
As shown in Figure 5-1, the timer is driven by the internal bus clock divided by four with a xed
prescaler. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be
read by the CPU at any time, by accessing the CTIMER counter register (CTCR) at address $09.
A timer overow function is implemented on the last stage of this counter, giving a possible
interrupt at the rate of fOP/1024. (The POR signal (tPORL) is also derived from this register, at
fOP/4064.) The counter register circuit is followed by four more stages, with the resulting clock
(fOP/16384) driving the real time interrupt circuit. The RTI circuit consists of three divider stages
with a 1-of-4 selector. The output of the RTI circuit is further divided by 8 to drive the COP
watchdog timer circuit. The RTI rate selector bits, and the RTI and CTIMER overow enable bits
and ags, are located in the CTIMER control and status register (CTCSR) at location $08.
CTOF (core timer overow ag) is a clearable, read-only status bit and is set when the 8-bit ripple
counter rolls over from $FF to $00. A CPU interrupt request will be generated if CTOFE is set.
Clearing the CTOF is done by writing a ‘0’ to it. Writing a ‘1’ to CTOF has no effect on the bit’s
value. Reset clears CTOF.
When CTOFE (core timer overow enable) is set, a CPU interrupt request is generated when the
CTOF bit is set. Reset clears CTOFE.
The core timer counter register (CTCR) is a read-only register that contains the current value of
the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at fOP/4 and can
be used for various functions including a software input capture. Extended time periods can be
attained using the CTIMER overow function to increment a temporary RAM storage location
thereby simulating a 16-bit (or more) counter.
The power-on cycle clears the entire counter chain and begins clocking the counter. After tPORL
cycles, the power-on reset circuit is released, which again clears the counter chain and allows the
device to come out of reset. At this point, if RESET is not asserted, the timer will start counting up
from zero and normal device operation will begin. When RESET is asserted at any time during
operation (other than POR), the counter chain will be cleared.
5.1
Real time interrupts (RTI)
The real time interrupt circuit consists of a three stage divider and a 1-of-4 selector. The clock
frequency that drives the RTI circuit is fOP/2
14 (or f
OP/16 384), with three additional divider stages,
giving a maximum interrupt period of 4 seconds at a bus frequency (fOP) of 32kHz. Register details
are given in Section 5.3.
5.2
Computer operating properly (COP) watchdog timer
The COP watchdog timer function is implemented by taking the output of the RTI circuit and
further dividing it by eight, as shown in Figure 5-1. Note that the minimum COP timeout period is
seven times the RTI period. This is because the COP will be cleared asynchronously with respect
TPG
33
相關(guān)PDF資料
PDF描述
MC68HC05J3P 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
MC68HC05J3DW 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
MC68HC05J3CP 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
MC68HC05J3DW 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
MC68HC05J3CDW 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
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