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參數(shù)資料
| 型號： | MC68HC05J3CDW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 52/74頁 |
| 文件大?。?/td> | 814K |
| 代理商： | MC68HC05J3CDW |
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MOTOROLA
7-6
MC68HC05J3
RESETS AND INTERRUPTS
7
7.4
Non-maskable software interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a non-maskable interrupt: it is
executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI
is executed after interrupts that were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specied by
the contents of memory locations $0FFC and $0FFD.
7.5
Maskable hardware interrupts
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are
masked. Clearing the I-bit allows interrupt processing to occur.
Note:
The internal interrupt latch is cleared in the rst part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the
I-bit is cleared.
7.5.1
External interrupt (IRQ or keyboard)
These external interrupt sources will vector to the same interrupt service routine, whose start
address is contained in memory locations $0FFA and $0FFB. IRQ can be selected to be either
edge sensitive or edge-and-level sensitive. Further details of the keyboard interrupt facility can be
found in Section 4.3.
7.5.2
Core timer interrupts
There are two core timer interrupt ags that cause an interrupt whenever an interrupt is enabled
and its ag becomes set (RTIF and CTOF). The interrupt ags and enable bits are located in the
core timer control and status register (CTCSR). These interrupts vector to the same interrupt
service routine, whose start address is contained in memory locations $0FF8 and $0FF9. Full
details of the core timer can be found in Section 5.
To make use of the real time interrupt, the RTIE bit must rst be set. The RTIF bit will then be set
after the specied number of counts.
To make use of the core timer overow interrupt, the CTOFE bit must rst be set. The CTOF bit
will then be set when the core timer counter register overows from $FF to $00.
TPG
53
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC05J3P | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
| MC68HC05J3DW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| MC68HC05J3CP | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20 |
| MC68HC05J3DW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| MC68HC05J3CDW | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05J3CP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit |
| MC68HC05J3DW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit |
| MC68HC05J3P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit |
| MC68HC05J5A | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-bit microcontroller units |
| MC68HC05J5ADW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-bit microcontroller units |
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