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| 型號： | MC68HC05J3DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 25/92頁 |
| 文件大小： | 912K |
| 代理商： | MC68HC05J3DW |
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MC68HC05J3
MOTOROLA
4-3
INPUT/OUTPUT PORTS
4
Reset does not affect the state of the data register, but clears the data direction register, thereby
returning all port pins to input mode. Writing a ‘1’ to any DDR bit sets the corresponding port pin
to output mode.
Provided that the interrupt mask bit of the condition code register is cleared, the keyboard interrupt
facility is enabled by setting the keyboard interrupt enable bit (KIE) in the port B conguration
register at location $07. The conguration register is described in Section 4.4.3.
Pins congured as output do not contribute to the wired-or interrupt. The structure of the port pins
is shown diagrammatically in Figure 4-2. When a low-to-high transition is detected on any of these
port pins, a keyboard interrupt request is generated and the port B interrupt status ag (KSF) is
set. The address of the interrupt service routine is specied by the contents of memory locations
$0FFA and $0FFB. Since this interrupt vector is shared with the IRQ external interrupt function,
the interrupt service routine should check KSF to determine the interrupt source. KSF can be
cleared by accessing the port B data register. The keyboard interrupt is edge sensitive. Care must
be taken to allow adequate time for switch debounce before clearing the ag.
A keyboard interrupt will force the MCU out of STOP or WAIT mode.
Figure 4-2 Port B keyboard interrupt function
+
IRQ
PB3
PB2
PB1
PB0
DDRB3
DDRB2
DDRB1
DDRB0
&
KIE
&
Internal
Edge
detect
interrupt
TPG
28
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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