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參數(shù)資料
| 型號： | MC68HC05J3DW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 32/92頁 |
| 文件大小： | 912K |
| 代理商： | MC68HC05J3DW |
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MOTOROLA
5-4
MC68HC05J3
CORE TIMER
5
RTIE — Real time interrupt enable
1 (set)
–
Real time interrupt is enabled.
0 (clear) –
Real time interrupt is disabled.
Setting this bit enables the real time interrupt. A CPU interrupt request will then be generated
whenever the RTIF bit becomes set. Clearing this bit disables the real time interrupt capability.
RT1:RT0 — Real time interrupt rate select
These two bits select one of four taps from the real time interrupt circuitry. Reset sets both RT0
and RT1 to one, selecting the lowest periodic rate and therefore the maximum time in which to
alter them if necessary. The COP reset times are also determined by these two bits. Care should
be taken when altering RT0 and RT1 if a timeout is imminent, or the timeout period is uncertain.
If the selected tap is modied during a cycle in which the counter is switching, an RTIF could be
missed or an additional one could be generated. To avoid problems, the COP should be cleared
before changing the RTI taps. See Table 5-1 for some example RTI periods.
5.3.2
Core timer counter register (CTCR)
The core timer counter register is a read-only register, which contains the current value of the 8-bit
ripple counter at the beginning of the timer chain. Reset clears this register.
Table 5-1 Example RTI periods
Bus frequency
fOP = 2 MHz
RT1 RT0
Division
ratio
RTI
period
Minimum
COP
period
0
214
8.2ms
57.3ms
0
1
215
16.4ms
114.7ms
1
0
216
32.8ms
229.4ms
1
217
65.5ms
458.8ms
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Core timer counter (CTCR)
$0009
TPG
35
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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