參數(shù)資料
型號: MC68HC05J3P
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 29/74頁
文件大?。?/td> 814K
代理商: MC68HC05J3P
MC68HC05J3
MOTOROLA
5-1
CORE TIMER
5
CORE TIMER
The MC68HC05J3 has a 15-stage ripple counter called the core timer (CTIMER). Features of this
timer are: timer overow; power-on reset (POR); real time interrupt (RTI), with four selectable
interrupt rates; and a computer operating properly (COP) watchdog timer.
Figure 5-1 Core timer block diagram
CTOF RTIF CTOFE RTIE
0
RT1
RT0
COP watchdog
timer
(
÷ 8 )
To
reset
logic
Overow
detect
circuit
(
÷ 4 )
To interrupt logic
Interrupt circuit
RTI select circuit
$09 CTCR
(Core timer counter)
$08 CTCSR
(Core timer control & status)
COP
clear
Internal processor clock
7-bit counter
fOP
fOP / 2
2
fOP / 2
10
fOP / 2
14
fOP / 2
17
Internal bus
8
TPG
32
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