參數(shù)資料
型號(hào): MC68HC05J3P
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝: PLASTIC, DIP-20
文件頁數(shù): 33/74頁
文件大?。?/td> 814K
代理商: MC68HC05J3P
MC68HC05J3
MOTOROLA
5-5
CORE TIMER
5
5.4
Core timer during WAIT
The CPU clock halts during the WAIT mode, but the core timer remains active. If the CTIMER
interrupts are enabled, then a CTIMER interrupt will cause the processor to exit the WAIT mode.
5.5
Core timer during STOP
The timer is cleared when going into STOP mode. When STOP is exited by an external interrupt
or an external reset, the internal oscillator will restart, followed by an internal processor
stabilization delay (tPORL). The timer is then cleared and operation resumes.
TPG
36
相關(guān)PDF資料
PDF描述
MC68HC05J3DW 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
MC68HC05J3CP 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
MC68HC05J3DW 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
MC68HC05J3CDW 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20
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