參數(shù)資料
型號(hào): MC68HC05J5AJDWR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16
封裝: SOIC-16
文件頁(yè)數(shù): 22/106頁(yè)
文件大小: 1069K
代理商: MC68HC05J5AJDWR2
GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
MEMORY
MC68HC05J5A
2-4
REV 2.1
ADDR
REGISTER
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
$0010
Port A Pull-down/up
R
PDURA
W
PURA7
PURA6
PDRA5
PDRA4
PDRA3
PDRA2
PDRA1
PDRA0
$0011
Port B Pull-down/up
R
PDURB
W
PDRB5
PDRB4
PDRB3
PURB2
PURB1
PDRB0
$0012
Timer1 Control
R
ICIE
0
T1OIE
000
IEDGE
0
T1CR
W
$0013
Timer1 Status
R
ICF
0
T1OF
00000
T1SR
W
$0014
Input Capture High
R
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
ICH
W
$0015
Input Capture Low
R
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
ICL
W
$0016
Unimplemented
R
W
$0017
Unimplemented
R
W
$0018
Timer1 Counter High
R
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
TCNTH
W
$0019
Timer1 Counter Low
R
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
TCNTL
W
$001A
Alt. Counter High
R
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
ACNTH
W
$001B
Alt. Counter Low
R
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
ACNTL
W
$001C
Unimplemented
R
W
$001D
Unimplemented
R
W
$001E
Reserved
R
W
$001F
Reserved
R
W
unimplemented bits
reserved bits
R
Figure 2-4. I/O Registers $0010-$001F
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