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參數(shù)資料
| 型號： | MC68HC05J5AJDWR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 69/106頁 |
| 文件大?。?/td> | 1069K |
| 代理商： | MC68HC05J5AJDWR2 |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
16-BIT TIMER
MOTOROLA
REV 2.1
9-7
Figure 9-9. TCAP Input Comparator Output
When the input capture circuitry detects an active edge on the TCAP pin, it
latches the contents of the free-running timer counter registers into the input cap-
ture registers as shown in Figure 9-6.
Latching values into the input capture registers at successive edges of the same
polarity measures the period of the selected input signal. Latching the counter val-
ues at successive edges of opposite polarity measures the pulse width of the sig-
nal.
The input capture registers are made up of two 8-bit read-only registers (ICH, ICL)
as shown in Figure 9-10. The input capture edge detector contains a Schmitt trig-
ger to improve noise immunity. The edge that triggers the counter transfer is
dened by the input edge bit (IEDG) in the T1CR. Reset does not affect the con-
tents of the input capture registers.
The result obtained by an input capture will be one count higher than the value of
the free-running timer counter preceding the external transition. This delay is
required for internal synchronization. Resolution is affected by the prescaler,
allowing the free-running timer counter to increment once every four internal clock
cycles (eight oscillator clock cycles).
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ICH
R
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
$0014
W
reset:
UUUUUUUU
ICL
R
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
$0015
W
reset:
UUUUUUUU
U = UNAFFECTED BY RESET
Figure 9-10. Input Capture Registers (ICH, ICL)
VDD ÷ 2
VDD
Output of Comparator
Signal on TCAP pin
Time
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