參數(shù)資料
型號(hào)： MC68HC05J5AJDWR2
廠(chǎng)商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁(yè)數(shù)： 71/106頁(yè)
文件大?。?/td> 1069K
代理商： MC68HC05J5AJDWR2
July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
16-BIT TIMER
MOTOROLA
REV 2.1
9-9
IEDG - INPUT CAPTURE EDGE SELECT
The state of this read/write bit determines whether a positive or negative transi-
tion on the TCAP pin triggers a transfer of the contents of the timer register to
the input capture register. Reset has no effect on the IEDG bit.
1 =
Positive edge (low to high transition) triggers input capture.
0 =
Negative edge (high to low transition) triggers input capture.
9.5
TIMER1 STATUS REGISTER (T1SR)
The timer status register (T1SR) shown in Figure 9-12 contains ags for the fol-
lowing events:
An active signal on the PB0/TCAP pin, transferring the contents of the
timer registers to the input capture registers.
An overow of the timer registers from $FFFF to $0000.
Writing to any of the bits in the T1SR has no effect. Reset does not change the
state of any of the ag bits in the T1SR.
ICF - INPUT CAPTURE FLAG
The ICF bit is automatically set when an edge of the selected polarity occurs on
the PB0/TCAP pin. Clear the ICF bit by reading the timer status register with
the ICF set, and then reading the low byte (ICL, $0015) of the input capture
registers. Reset has no effect on ICF.
T1OF - TIMER1 OVERFLOW FLAG
The T1OF bit is automatically set when the 16-bit timer counter rolls over from
$FFFF to $0000. Clear the T1OF bit by reading the timer status register with
the T1OF set, and then accessing the low byte (TCNTL, $0019) of the timer
registers. Reset has no effect on T1OF.
9.6
TIMER1 OPERATION DURING WAIT MODE
During WAIT mode the 16-bit timer continues to operate normally and may gener-
ate an interrupt to trigger the MCU out of the WAIT mode.
9.7
TIMER1 OPERATION DURING STOP MODE
When the MCU enters the STOP mode the free-running counter stops counting
(the internal processor clock is stopped). It remains at that particular count value
until the STOP mode is exited by applying a low signal to the IRQ pin, at which
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
T1SR
R
ICF
0
T1OF
00000
$0013
W
reset:
U
00000
U = UNAFFECTED BY RESET
Figure 9-12. Timer Status Registers (T1SR)
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