參數(shù)資料
型號： MC68HC05J5CJDW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 13/69頁
文件大小： 394K
代理商： MC68HC05J5CJDW
GENERAL RELEASE SPECIFICATION
December 11, 1996
MOTOROLA
MEMORY
MC68HC05J5
2-2
REV 1.1
2.2
I/O AND CONTROL REGISTERS
The I/O and Control Registers reside in locations $0000-$001F. The overall orga-
nization of these registers is shown in Figure 2-2. The bit assignments for each
register are shown in Figure 2-3 and Figure 2-4. Reading from unimplemented
bits will return unknown states, and writing to unimplemented bits will be ignored.
Figure 2-2. I/O Registers Memory Map
2.3
RAM
The User RAM consists of 64 bytes (including the stack), located from $00C0 to
$00FF. The stack begins at address $00FF and proceeds down to $00C0. Using
the stack area for data storage or temporary work locations requires care to pre-
vent it from being overwritten due to stacking from an interrupt or subroutine call.
2.4
ROM
There are a total of 1240 bytes of user ROM on-chip. This includes 1232 bytes of
user ROM from locations $0300 to $07CF for user program storage and 8 bytes
for user vectors from locations $07F8 to $07FF. There are a total of 40 bytes of
Internal Test ROM on chip at locations $07D0 to $07EF and from $07F0 to $07F7.
Port A Data Register
$0000
Port B Data Register
$0001
Port A Data Direction Register
$0004
Port B Data Direction Register
$0005
Timer Control & Status Register
$0008
Timer Counter Register
$0009
Reserved
$001F
unimplemented (2 bytes)
unimplemented (5 bytes)
unimplemented (13 bytes)
IRQ Control & Status Register
$000A
Port A Pull-down/up Register
$0010
Port B Pull-down/up Register
$0011
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