參數(shù)資料
型號(hào)： MC68HC05J5CJDW
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁(yè)數(shù)： 55/69頁(yè)
文件大?。?/td> 394K
代理商： MC68HC05J5CJDW
December 11, 1996
GENERAL RELEASE SPECIFICATION
MC68HC05J5
INSTRUCTION SET
MOTOROLA
REV 1.1
9-5
9.6.6 Indexed, 8-bit Offset
In the indexed, 8-bit offset addressing mode, the effective address is the sum of
the contents of the unsigned 8-bit index register and the unsigned byte following
the opcode. The addressing mode is useful for selecting the Kth element in an ele-
ment table. With this two-byte instruction, K would typically be in X with the
address of the beginning of the table in the instruction. As such, tables may begin
anywhere within the rst 256 addressable locations and could extend as far as
location 510. $1FE is the highest location which can be accessed in this way.
9.6.7 Indexed, 16-bit Offset
In the indexed, 16-bit offset addressing mode, the effective address is the sum of
the contents of the unsigned 8-bit index register and the two unsigned bytes fol-
lowing the opcode. This address mode can be used in a manner similar to
indexed, 8-bit offset except that this three-byte instruction allows tables to be any-
where in memory. As with direct and extended addressing, the Motorola assem-
bler determines the shortest form of indexed addressing.
9.6.8 Bit Set/Clear
In the bit set/clear addressing mode, the bit to be set or cleared is part of the
opcode, and the byte following the opcode species the direct address of the byte
in which the specied bit is to be set or cleared. Any read/write register bit in the
rst 256 locations of memory, including I/O, can by selectively set or cleared with a
single two-byte instruction.
9.6.9 Bit Test and Branch
The bit test and branch addressing mode is a combination of direct addressing
and relative addressing. The bit that is to be tested and its condition (set or clear),
is included in the opcode. The address of the byte to be tested is in the single byte
immediately following the opcode byte. The signed relative 8-bit offset in the third
byte is added to the PC if the specied bit is set or cleared in the specied mem-
ory location. This single three-byte instruction allows the program to branch based
on the condition of any readable bit in the rst 256 locations of memory. The span
of branching is from -128 to +127 from the address of the next opcode. The state
of the tested bit is also transferred to the carry bit of the condition code register.
9.6.10 Inherent
In the inherent addressing mode, all the information necessary to execute the
instruction is contained in the opcode. Operations specifying only the index regis-
ter and/or accumulator as well as the control instructions with no other arguments
are included in this mode. These instructions are one byte long.
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