參數(shù)資料
型號(hào): MC68HC05K3CSDR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO20
封裝: SSOP-20
文件頁數(shù): 113/132頁
文件大小: 1188K
代理商: MC68HC05K3CSDR2
Personality EEPROM (PEEPROM)
PEEPROM Registers
MC68HC05K3 — Revision 4.0
Technical Data
MOTOROLA
Personality EEPROM (PEEPROM)
81
9.3 PEEPROM Registers
Two register locations are used to support the EEPROM array. These
are the bit select and status/control registers.
9.3.1 PEEPROM Bit Select Register
The PEEPROM bit select register (PEBSR) is located at $000E and
contains the enable signals for the rows and columns to access the bits
in the EEPROM array. Figure 9-2 shows the placement of these bits.
The output of this register is connected to two decoders, one for the
array column and one for the array row.
A byte in the PEEPROM is defined by the upper four bits in the 7-bit
address in the PEBSR (PEB3–PEB6) and the bit within that byte is
defined by the lower three bits in the 7-bit address in the PEBSR
(PEB0–PEB2). The upper bit in the PEBSR (PEB7) may be used as a
storage location. All of the bits in the PEBSR register are cleared by
reset.
Address:
$000E
Byte (Row) of PEEPROM
Bit (Column in Byte (Row)
of PEEPROM
3210
2
1
0
Bit 7
6543
2
1
Bit 0
Read:
PEB7
PEB6
PEB5
PEB4
PEB3
PEB2
PEB1
PEB0
Write:
Reset:
00000
0
Figure 9-2. PEEPROM Bit Select Register (PEBSR)
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