參數(shù)資料
型號(hào): MC68HC05K3CSDR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO20
封裝: SSOP-20
文件頁數(shù): 79/132頁
文件大?。?/td> 1188K
代理商: MC68HC05K3CSDR2
Technical Data
MC68HC05K3 — Revision 4.0
50
Resets
MOTOROLA
Resets
Figure 5-1. Reset Block Diagram
5.3 External Reset (RESET)
The RESET pin is the only external source of a reset. This pin is
connected to a Schmitt trigger input gate to provide noise immunity. This
external reset occurs whenever the RESET pin is pulled low and
remains in reset until the RESET pin rises to a logic 1. This active low
input generates the RST signal and resets the CPU and peripherals.
5.4 Internal Resets
The three internally generated resets are:
Initial power-on reset (POR) function
Computer operating properly (COP) watchdog timer reset
Illegal address detector reset (ILADR)
5.4.1 Power-On Reset (POR)
The internal POR is generated on power-up of the internal CPU to allow
the clock oscillator to stabilize. The POR is strictly for power turn-on
conditions and is not able to detect a drop in the power supply voltage (a
VDD
RST
ILLEGAL ADDRESS
(ILADR)
CPU
LATCH
RESET
COP WATCHDOG
RESET (COPR)
OSC
DATA
ADDRESS
PH2
TO OTHER
PERIPHERALS
S
POWER-ON RESET
(POR)
VDD
ADDRESS
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