參數(shù)資料
型號: MC68HC05K3CSDR2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDSO20
封裝: SSOP-20
文件頁數(shù): 22/132頁
文件大?。?/td> 1188K
代理商: MC68HC05K3CSDR2
Technical Data
MC68HC05K3 — Revision 4.0
118
Electrical Specifications
MOTOROLA
Electrical Specications
11.6 5.0-Volt DC Electrical Characteristics
Characteristic(1)
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
Symbol
Min(2)
2. All values shown reflect average measurements.
Typ(3)
3. Typical values at midpoint of voltage range, 25
°C only
Max
Unit
Output high voltage (ILoad = –0.8 mA)
PA7–PA0, PB1/OSC3, PB0
VOH
V
DD –0.8
——
V
Output low voltage
PA3–PA0, PB1/OSC3, PB0 (ILoad = 1.6 mA)
PA7–PA4 (ILoad = 8.0 mA)
VOL
0.4
V
Input high voltage
PA0–PA7, PB0, PB1/OSC3, IRQ, RESET, OSC1
VIH
0.7 x V
DD
V
DD
V
Input low voltage
PA0–PA7, PB0, PB1/OSC3, IRQ, RESET, OSC1
VIL
V
SS
0.2 x V
DD
V
Supply current (f
OP = 2 MHz)
(4), (5), (6), (7), (8)
Run
Wait
Stop
25
°C
0
°C to +70 °C (standard)
–40
°C to +85 °C (extended)
4. Wait IDD: Only timer system active
5. Run (operating) IDD, wait IDD: Measured using external square wave clock source to OSC1, all inputs 0.2 Vdc from rail;
no DC loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
6. Wait, stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc
7. Stop IDD measured with OSC1 = VDD, RESET open
8. Wait IDD is affected linearly by the OSC2 capacitance.
IDD
100
5.0
3.0
200
400
500
mA
nA
I/O ports hi-Z leakage current
PA0–PA7, PB0–PB1 (without pulldowns activated)
IIL
0.2
1
A
Input pulldown current
PA0–PA7, PB0–PB1
IIL
50
100
200
A
Input current IRQ and OSC1
RESET (VIn = VIH)
RESET (VIn = VIL)
IIn
15
50
1
A
RESET, internal pulldown device
IIn
1.0
4.0
8.0
mA
Capacitance
Ports (as input or output)
RESET, IRQ, OSC1, OSC2
COut
CIn
12
8
pF
Crystal/ceramic resonator
Oscillator mode internal resistor OSC1 to OSC2
ROSC
1.0
2.0
3.0
M
Notes:
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